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| author | Tim Newsome <tim@sifive.com> | 2017-09-25 11:05:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-09-25 11:05:36 -0700 |
| commit | 58b6c187df1a5cc066c97a63483d297fd159f241 (patch) | |
| tree | 16744923a356a6e2ca3f399562000394538a5cc6 | |
| parent | b86f2a51f522f020ad0d90f598f4c501f41da232 (diff) | |
| parent | def8b3e05d754c8115deb0c8b8c91dc4e33975fd (diff) | |
| download | spike-58b6c187df1a5cc066c97a63483d297fd159f241.zip spike-58b6c187df1a5cc066c97a63483d297fd159f241.tar.gz spike-58b6c187df1a5cc066c97a63483d297fd159f241.tar.bz2 | |
Merge pull request #128 from riscv/reset
Fix debug reset.
| -rw-r--r-- | riscv/debug_module.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 53df8a4..985cbbd 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -447,6 +447,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) if (dmcontrol.dmactive) { dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ); dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ); + dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET); dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET); dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL); } else { @@ -459,10 +460,16 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME); resumeack[dmcontrol.hartsel] = false; } - if (dmcontrol.ndmreset) { + if (dmcontrol.hartreset) { proc->reset(); } } + if (dmcontrol.ndmreset) { + for (size_t i = 0; i < sim->nprocs(); i++) { + proc = sim->get_core(i); + proc->reset(); + } + } } return true; |