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authorTim Newsome <tim@sifive.com>2017-09-21 12:34:42 -0700
committerTim Newsome <tim@sifive.com>2017-09-21 13:20:29 -0700
commit526d3997e68200ef3f372384acdc13e8e8b92e31 (patch)
tree7303d00b2380d8e896188bd8b4b5399ec37bcdf3
parentb86f2a51f522f020ad0d90f598f4c501f41da232 (diff)
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Fix debug reset.
ndmreset now resets all harts (instead of just the current hart), and hartreset resets the selected hart (instead of being ignored).
-rw-r--r--riscv/debug_module.cc8
1 files changed, 7 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 53df8a4..8d73f07 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -459,10 +459,16 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
resumeack[dmcontrol.hartsel] = false;
}
- if (dmcontrol.ndmreset) {
+ if (dmcontrol.hartreset) {
proc->reset();
}
}
+ if (dmcontrol.ndmreset) {
+ for (size_t i = 0; i < sim->nprocs(); i++) {
+ proc = sim->get_core(i);
+ proc->reset();
+ }
+ }
}
return true;