Simplify vfwcvt

8 files changed, 112 insertions, 195 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 541b46b..9058334 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2423,6 +2423,56 @@ reg_t index[P.VU.vlmax]; \
       break; \
   }
 
+#define VI_VFP_WCVT_FP_TO_FP(BODY8, BODY16, BODY32, \
+                             CHECK8, CHECK16, CHECK32) \
+  VI_CHECK_DSS(false); \
+  switch(P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(16, 32), CHECK16, BODY16); } \
+      break; \
+    case e32: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 64), CHECK32, BODY32); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
+#define VI_VFP_WCVT_INT_TO_FP(BODY8, BODY16, BODY32, \
+                              CHECK8, CHECK16, CHECK32, \
+                              sign) \
+  VI_CHECK_DSS(false); \
+  switch(P.VU.vsew) { \
+    case e8: \
+      { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(8, 16, sign), CHECK8, BODY8); } \
+      break; \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 32, sign), CHECK16, BODY16); } \
+      break; \
+    case e32: \
+      { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 64, sign), CHECK32, BODY32); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
+#define VI_VFP_WCVT_FP_TO_INT(BODY8, BODY16, BODY32, \
+                              CHECK8, CHECK16, CHECK32, \
+                              sign) \
+  VI_CHECK_DSS(false); \
+  switch(P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 32, sign), CHECK16, BODY16); } \
+      break; \
+    case e32: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 64, sign), CHECK32, BODY32); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
 #define VI_VFP_NCVT_FP_TO_FP(BODY8, BODY16, BODY32, \
                             CHECK8, CHECK16, CHECK32) \
   VI_CHECK_SDS(false); \
@@ -2473,45 +2523,6 @@ reg_t index[P.VU.vlmax]; \
       break; \
   }
 
-#define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, \
-                         CHECK8, CHECK16, CHECK32, \
-                         is_widen, eew_check) \
-  if (is_widen) { \
-    VI_CHECK_DSS(false);\
-  } else { \
-    VI_CHECK_SDS(false); \
-  } \
-  require(eew_check); \
-  switch(P.VU.vsew) { \
-    case e8: {\
-      CHECK8 \
-      VI_VFP_LOOP_SCALE_BASE \
-        BODY8 \
-        set_fp_exceptions; \
-      VI_VFP_LOOP_END \
-      } \
-      break; \
-    case e16: {\
-      CHECK16 \
-      VI_VFP_LOOP_SCALE_BASE \
-        BODY16 \
-        set_fp_exceptions; \
-      VI_VFP_LOOP_END \
-      } \
-      break; \
-    case e32: {\
-      CHECK32 \
-      VI_VFP_LOOP_SCALE_BASE \
-        BODY32 \
-        set_fp_exceptions; \
-      VI_VFP_LOOP_END \
-      } \
-      break; \
-    default: \
-      require(0); \
-      break; \
-  }
-
 // The p-extension support is contributed by
 // Programming Langauge Lab, Department of Computer Science, National Tsing-Hua University, Taiwan
 
diff --git a/riscv/insns/vfwcvt_f_f_v.h b/riscv/insns/vfwcvt_f_f_v.h
index fcaf65c..0700070 100644
--- a/riscv/insns/vfwcvt_f_f_v.h
+++ b/riscv/insns/vfwcvt_f_f_v.h
@@ -1,23 +1,9 @@
 // vfwcvt.f.f.v vd, vs2, vm
-VI_VFP_CVT_SCALE
-({
-  ;
-},
-{
-  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
-  P.VU.elt<float32_t>(rd_num, i, true) = f16_to_f32(vs2);
-},
-{
-  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
-  P.VU.elt<float64_t>(rd_num, i, true) = f32_to_f64(vs2);
-},
-{
-  ;
-},
-{
-  require(p->extension_enabled(EXT_ZFH));
-},
-{
-  require(p->extension_enabled('D'));
-},
-true, (P.VU.vsew >= 16))
+VI_VFP_WCVT_FP_TO_FP(
+  {;},                             // BODY8
+  { vd = f16_to_f32(vs2); },       // BODY16
+  { vd = f32_to_f64(vs2); },       // BODY32
+  {;},                             // CHECK8
+  { require_extension(EXT_ZFH); }, // CHECK16
+  { require_extension('D'); }      // CHECK32
+)
diff --git a/riscv/insns/vfwcvt_f_x_v.h b/riscv/insns/vfwcvt_f_x_v.h
index 8d8283c..f51e8e3 100644
--- a/riscv/insns/vfwcvt_f_x_v.h
+++ b/riscv/insns/vfwcvt_f_x_v.h
@@ -1,24 +1,10 @@
 // vfwcvt.f.x.v vd, vs2, vm
-VI_VFP_CVT_SCALE
-({
-  auto vs2 = P.VU.elt<int8_t>(rs2_num, i);
-  P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2);
-},
-{
-  auto vs2 = P.VU.elt<int16_t>(rs2_num, i);
-  P.VU.elt<float32_t>(rd_num, i, true) = i32_to_f32(vs2);
-},
-{
-  auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
-  P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
-},
-{
-  require(p->extension_enabled(EXT_ZFH));
-},
-{
-  require(p->extension_enabled('F'));
-},
-{
-  require(p->extension_enabled('D'));
-},
-true, (P.VU.vsew >= 8))
+VI_VFP_WCVT_INT_TO_FP(
+  { vd = i32_to_f16(vs2); },                   // BODY8
+  { vd = i32_to_f32(vs2); },                   // BODY16
+  { vd = i32_to_f64(vs2); },                   // BODY32
+  { require(p->extension_enabled(EXT_ZFH)); }, // CHECK8
+  { require_extension('F'); },                 // CHECK16
+  { require_extension('D'); },                 // CHECK32
+  int                                          // sign
+)
diff --git a/riscv/insns/vfwcvt_f_xu_v.h b/riscv/insns/vfwcvt_f_xu_v.h
index e8036ce..7dd4972 100644
--- a/riscv/insns/vfwcvt_f_xu_v.h
+++ b/riscv/insns/vfwcvt_f_xu_v.h
@@ -1,24 +1,10 @@
 // vfwcvt.f.xu.v vd, vs2, vm
-VI_VFP_CVT_SCALE
-({
-  auto vs2 = P.VU.elt<uint8_t>(rs2_num, i);
-  P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2);
-},
-{
-  auto vs2 = P.VU.elt<uint16_t>(rs2_num, i);
-  P.VU.elt<float32_t>(rd_num, i, true) = ui32_to_f32(vs2);
-},
-{
-  auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
-  P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
-},
-{
-  require(p->extension_enabled(EXT_ZFH));
-},
-{
-  require(p->extension_enabled('F'));
-},
-{
-  require(p->extension_enabled('D'));
-},
-true, (P.VU.vsew >= 8))
+VI_VFP_WCVT_INT_TO_FP(
+  { vd = ui32_to_f16(vs2); },                   // BODY8
+  { vd = ui32_to_f32(vs2); },                   // BODY16
+  { vd = ui32_to_f64(vs2); },                   // BODY32
+  { require(p->extension_enabled(EXT_ZFH)); },  // CHECK8
+  { require_extension('F'); },                  // CHECK16
+  { require_extension('D'); },                  // CHECK32
+  uint                                          // sign
+)
diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h
index 83fa764..74e5b9a 100644
--- a/riscv/insns/vfwcvt_rtz_x_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_x_f_v.h
@@ -1,23 +1,10 @@
 // vfwcvt.rtz.x.f.v vd, vs2, vm
-VI_VFP_CVT_SCALE
-({
-  ;
-},
-{
-  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
-  P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, softfloat_round_minMag, true);
-},
-{
-  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
-  P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, softfloat_round_minMag, true);
-},
-{
-  ;
-},
-{
-  require(p->extension_enabled(EXT_ZFH));
-},
-{
-  require(p->extension_enabled('F'));
-},
-true, (P.VU.vsew >= 16))
+VI_VFP_WCVT_FP_TO_INT(
+  {;},                                                     // BODY8
+  { vd = f16_to_i32(vs2, softfloat_round_minMag, true); }, // BODY16
+  { vd = f32_to_i64(vs2, softfloat_round_minMag, true); }, // BODY32
+  {;},                                                     // CHECK8
+  { require_extension(EXT_ZFH); },                         // CHECK16
+  { require_extension('F'); },                             // CHECK32
+  int                                                      // sign
+)
diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h
index 43d1979..72b8c6e 100644
--- a/riscv/insns/vfwcvt_rtz_xu_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h
@@ -1,23 +1,10 @@
 // vfwcvt.rtz,xu.f.v vd, vs2, vm
-VI_VFP_CVT_SCALE
-({
-  ;
-},
-{
-  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
-  P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, softfloat_round_minMag, true);
-},
-{
-  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
-  P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, softfloat_round_minMag, true);
-},
-{
-  ;
-},
-{
-  require(p->extension_enabled(EXT_ZFH));
-},
-{
-  require(p->extension_enabled('F'));
-},
-true, (P.VU.vsew >= 16))
+VI_VFP_WCVT_FP_TO_INT(
+  {;},                                                      // BODY8
+  { vd = f16_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY16
+  { vd = f32_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY32
+  {;},                                                      // CHECK8
+  { require_extension(EXT_ZFH); },                          // CHECK16
+  { require_extension('F'); },                              // CHECK32
+  uint                                                      // sign
+)
diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h
index 5e0c064..74497f4 100644
--- a/riscv/insns/vfwcvt_x_f_v.h
+++ b/riscv/insns/vfwcvt_x_f_v.h
@@ -1,23 +1,10 @@
 // vfwcvt.x.f.v vd, vs2, vm
-VI_VFP_CVT_SCALE
-({
-  ;
-},
-{
-  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
-  P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, STATE.frm->read(), true);
-},
-{
-  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
-  P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm->read(), true);
-},
-{
-  ;
-},
-{
-  require(p->extension_enabled(EXT_ZFH));
-},
-{
-  require(p->extension_enabled('F'));
-},
-true, (P.VU.vsew >= 16))
+VI_VFP_WCVT_FP_TO_INT(
+  {;},                                                     // BODY8
+  { vd = f16_to_i32(vs2, softfloat_roundingMode, true); }, // BODY16
+  { vd = f32_to_i64(vs2, softfloat_roundingMode, true); }, // BODY32
+  {;},                                                     // CHECK8
+  { require_extension(EXT_ZFH); },                         // CHECK16
+  { require_extension('F'); },                             // CHECK32
+  int                                                      // sign
+)
diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h
index f3243c8..ad96c9c 100644
--- a/riscv/insns/vfwcvt_xu_f_v.h
+++ b/riscv/insns/vfwcvt_xu_f_v.h
@@ -1,23 +1,10 @@
 // vfwcvt.xu.f.v vd, vs2, vm
-VI_VFP_CVT_SCALE
-({
-  ;
-},
-{
-  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
-  P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, STATE.frm->read(), true);
-},
-{
-  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
-  P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm->read(), true);
-},
-{
-  ;
-},
-{
-  require(p->extension_enabled(EXT_ZFH));
-},
-{
-  require(p->extension_enabled('F'));
-},
-true, (P.VU.vsew >= 16))
+VI_VFP_WCVT_FP_TO_INT(
+  {;},                                                      // BODY8
+  { vd = f16_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY16
+  { vd = f32_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY32
+  {;},                                                      // CHECK8
+  { require_extension(EXT_ZFH); },                          // CHECK16
+  { require_extension('F'); },                              // CHECK32
+  uint                                                      // sign
+)