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author | Andrew Waterman <andrew@sifive.com> | 2022-01-09 17:04:17 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-01-09 17:05:07 -0800 |
commit | d1a3a4255295b742728b8c851a222cfbf06e8116 (patch) | |
tree | 22b1f5d3175faff032308b4f4cc1bb187cc9498d | |
parent | 39fc8c3921e8c9ffd9996a7d59df239b2488a206 (diff) | |
download | spike-d1a3a4255295b742728b8c851a222cfbf06e8116.zip spike-d1a3a4255295b742728b8c851a222cfbf06e8116.tar.gz spike-d1a3a4255295b742728b8c851a222cfbf06e8116.tar.bz2 |
Changes to be cleaner wrt. -Wextra
h/t @jerinjoy
See #901
-rw-r--r-- | riscv/debug_module.cc | 10 | ||||
-rw-r--r-- | riscv/decode.h | 2 | ||||
-rw-r--r-- | riscv/disasm.h | 2 | ||||
-rw-r--r-- | riscv/interactive.cc | 6 | ||||
-rw-r--r-- | riscv/processor.cc | 1 |
5 files changed, 10 insertions, 11 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index ef25b4d..10ff9bb 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -87,20 +87,20 @@ void debug_module_t::reset() proc->halt_request = proc->HR_NONE; } - dmcontrol = {0}; + memset(&dmcontrol, 0, sizeof(dmcontrol)); - dmstatus = {0}; + memset(&dmstatus, 0, sizeof(dmstatus)); dmstatus.impebreak = config.support_impebreak; dmstatus.authenticated = !config.require_authentication; dmstatus.version = 2; - abstractcs = {0}; + memset(&abstractcs, 0, sizeof(abstractcs)); abstractcs.datacount = sizeof(dmdata) / 4; abstractcs.progbufsize = config.progbufsize; - abstractauto = {0}; + memset(&abstractauto, 0, sizeof(abstractauto)); - sbcs = {0}; + memset(&sbcs, 0, sizeof(sbcs)); if (config.max_sba_data_width > 0) { sbcs.version = 1; sbcs.asize = sizeof(reg_t) * 8; diff --git a/riscv/decode.h b/riscv/decode.h index 3b3cf54..e709d03 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -186,7 +186,7 @@ private: #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) -# define WRITE_VSTATUS +# define WRITE_VSTATUS {} #else /* 0 : int * 1 : floating diff --git a/riscv/disasm.h b/riscv/disasm.h index e7cee6b..0f528a3 100644 --- a/riscv/disasm.h +++ b/riscv/disasm.h @@ -97,7 +97,7 @@ class disassembler_t static const unsigned int MASK1 = 0x7f; static const unsigned int MASK2 = 0xe003; - static const unsigned int hash(insn_bits_t insn, unsigned int mask) + static unsigned int hash(insn_bits_t insn, unsigned int mask) { return (insn & mask) % HASH_SIZE; } diff --git a/riscv/interactive.cc b/riscv/interactive.cc index dc6837d..172cd33 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -50,11 +50,9 @@ static std::string readline(int fd) continue; s.erase(s.end()-1); - if (noncanonical && write(fd, "\b \b", 3) != 3) - ; // shut up gcc + if (noncanonical && write(fd, "\b \b", 3) != 3) {} } - else if (noncanonical && write(fd, &ch, 1) != 1) - ; // shut up gcc + else if (noncanonical && write(fd, &ch, 1) != 1) {} if (ch == '\n') break; diff --git a/riscv/processor.cc b/riscv/processor.cc index e7e60bf..61197a5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -234,6 +234,7 @@ void processor_t::parse_isa_string(const char* str) extension_table[EXT_ZPSFOPERAND] = true; extension_table[EXT_ZMMUL] = true; break; case 'q': max_isa |= 1L << ('d' - 'a'); + // Fall through case 'd': max_isa |= 1L << ('f' - 'a'); } max_isa |= 1L << (*p - 'a'); |