diff options
| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-08-07 17:27:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-08-07 17:27:25 -0700 |
| commit | e2c0c3021ac2fa7cad5866e0f100c2dbf2372986 (patch) | |
| tree | 341275e3db57ae87224f2e6365a836b74afa4f69 | |
| parent | dca8e36deec90049d1642f27490f2e8089a639a8 (diff) | |
| download | spike-e2c0c3021ac2fa7cad5866e0f100c2dbf2372986.zip spike-e2c0c3021ac2fa7cad5866e0f100c2dbf2372986.tar.gz spike-e2c0c3021ac2fa7cad5866e0f100c2dbf2372986.tar.bz2 | |
Support uarch counters (degenerately)
| -rw-r--r-- | riscv/processor.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 8ba87ed..4b282f6 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -353,6 +353,23 @@ reg_t processor_t::get_pcr(int which) case CSR_FROMHOST: sim->get_htif()->tick(); // not necessary, but faster return state.fromhost; + case CSR_UARCH0: + case CSR_UARCH1: + case CSR_UARCH2: + case CSR_UARCH3: + case CSR_UARCH4: + case CSR_UARCH5: + case CSR_UARCH6: + case CSR_UARCH7: + case CSR_UARCH8: + case CSR_UARCH9: + case CSR_UARCH10: + case CSR_UARCH11: + case CSR_UARCH12: + case CSR_UARCH13: + case CSR_UARCH14: + case CSR_UARCH15: + return 0; } throw trap_illegal_instruction(); } |