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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-06-12 14:16:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-06-12 14:16:27 -0700 |
| commit | 013657ac8c0ac0c4c2582d3073f1ef180f1c5a02 (patch) | |
| tree | 1620e336538a09cde797434d5425c7f640cabac0 | |
| parent | acc42d79e283a31de4037fcf75d9e8af61073b51 (diff) | |
| download | spike-013657ac8c0ac0c4c2582d3073f1ef180f1c5a02.zip spike-013657ac8c0ac0c4c2582d3073f1ef180f1c5a02.tar.gz spike-013657ac8c0ac0c4c2582d3073f1ef180f1c5a02.tar.bz2 | |
Set status.u64 to true on boot
This isn't required by the ISA but it matches existing HW.
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index f47c8e5..8cece3e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -40,7 +40,7 @@ void state_t::reset() // the ISA guarantees on boot that the PC is 0x2000 and the the processor // is in supervisor mode, and in 64-bit mode, if supported, with traps // and virtual memory disabled. - sr = SR_S | SR_S64; + sr = SR_S | SR_S64 | SR_U64; pc = 0x2000; // the following state is undefined upon boot-up, |