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authorAbhinay Kayastha <abhinay.kayastha@sifive.com>2020-07-06 17:02:05 -0700
committerAbhinay Kayastha <abhinay.kayastha@sifive.com>2020-07-06 17:02:05 -0700
commit85b7e37d013ef2f1a505ffc00d142f26dcf81d80 (patch)
treedea16a5418f8faf22b2b6491b3dcd69216c9a5b0
parent4ae887c1ffd54f9e33461bbe6774693eb41267a0 (diff)
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If n_pmp=0, then pmp is not implemented hence raise trap
-rw-r--r--riscv/processor.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index d6348a8..9dc5911 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1047,6 +1047,9 @@ reg_t processor_t::get_csr(int which)
return 0;
if (which >= CSR_PMPADDR0 && which < CSR_PMPADDR0 + state.max_pmp) {
+ // If n_pmp is zero, that means pmp is not implemented hence raise trap if it tries to access the csr
+ if (n_pmp == 0)
+ throw trap_illegal_instruction(0);
reg_t i = which - CSR_PMPADDR0;
if ((state.pmpcfg[i] & PMP_A) >= PMP_NAPOT)
return state.pmpaddr[i] | (~pmp_tor_mask() >> 1);