Merge pull request #519 from chihminchao/rvv-pre-1.0

Rvv pre 1.0

64 files changed, 483 insertions, 282 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index e7642e6..9f8f786 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -118,8 +118,8 @@ public:
   uint64_t v_zimm5() { return x(15, 5); }
   uint64_t v_zimm11() { return x(20, 11); }
   uint64_t v_lmul() { return x(20, 2); }
+  uint64_t v_frac_lmul() { return x(22, 1); }
   uint64_t v_sew() { return 1 << (x(23, 3) + 3); }
-  uint64_t v_frac_lmul() { return x(23, 1); }
   uint64_t v_width() { return x(12, 3); }
   uint64_t v_mop() { return x(26, 2); }
   uint64_t v_lumop() { return x(20, 5); }
@@ -303,7 +303,7 @@ class wait_for_interrupt_t {};
 
 /* Convenience wrappers to simplify softfloat code sequences */
 #define isBoxedF16(r) (isBoxedF32(r) && ((uint64_t)((r.v[0] >> 16) + 1) == ((uint64_t)1 << 48)))
-#define unboxF16(r) (isBoxedF16(r) ? (uint32_t)r.v[0] : defaultNaNF16UI)
+#define unboxF16(r) (isBoxedF16(r) ? (uint16_t)r.v[0] : defaultNaNF16UI)
 #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0))
 #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI)
 #define isBoxedF64(r) ((r.v[1] + 1) == 0)
@@ -484,32 +484,29 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 
 #define VI_CHECK_ST_INDEX(elt_width) \
   require_vector; \
-  P.VU.veew = elt_width; \
-  P.VU.vemul = ((float)P.VU.veew / P.VU.vsew * P.VU.vflmul); \
-  require(P.VU.vemul >= 0.125 && P.VU.vemul <= 8); \
-  reg_t emul = P.VU.vemul < 1 ? 1 : P.VU.vemul; \
+  float vemul = ((float)elt_width / P.VU.vsew * P.VU.vflmul); \
+  require(vemul >= 0.125 && vemul <= 8); \
+  reg_t emul = vemul < 1 ? 1 : vemul; \
   reg_t flmul = P.VU.vflmul < 1 ? 1 : P.VU.vflmul; \
   require_align(insn.rd(), P.VU.vflmul); \
-  require_align(insn.rs2(), P.VU.vemul); \
+  require_align(insn.rs2(), vemul); \
   require((nf * flmul) <= (NVPR / 4) && \
           (insn.rd() + nf * flmul) <= NVPR); \
-  if (nf > 1) \
-    require(p->supports_extension(EXT_ZVLSSEG)); \
 
 #define VI_CHECK_LD_INDEX(elt_width) \
   VI_CHECK_ST_INDEX(elt_width); \
-  if (P.VU.veew > P.VU.vsew) { \
+  if (elt_width > P.VU.vsew) { \
     if (insn.rd() != insn.rs2()) \
-      require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
-  } else if (P.VU.veew < P.VU.vsew) { \
-    if (P.VU.vemul < 1) {\
-      require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
+      require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \
+  } else if (elt_width < P.VU.vsew) { \
+    if (vemul < 1) {\
+      require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \
     } else {\
-      require_noover_widen(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
+      require_noover_widen(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \
     } \
   } \
   if (insn.v_nf() > 0) {\
-    require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
+    require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \
     require_noover(vd, nf, insn.rs2(), 1); \
   } \
   require_vm; \
@@ -536,15 +533,13 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 
 #define VI_CHECK_STORE(elt_width) \
   require_vector; \
-  P.VU.veew = sizeof(elt_width##_t) * 8; \
-  P.VU.vemul = ((float)P.VU.veew / P.VU.vsew * P.VU.vflmul); \
-  reg_t emul = P.VU.vemul < 1 ? 1 : P.VU.vemul; \
-  require(P.VU.vemul >= 0.125 && P.VU.vemul <= 8); \
-  require_align(insn.rd(), P.VU.vemul); \
+  reg_t veew = sizeof(elt_width##_t) * 8; \
+  float vemul = ((float)veew / P.VU.vsew * P.VU.vflmul); \
+  reg_t emul = vemul < 1 ? 1 : vemul; \
+  require(vemul >= 0.125 && vemul <= 8); \
+  require_align(insn.rd(), vemul); \
   require((nf * emul) <= (NVPR / 4) && \
           (insn.rd() + nf * emul) <= NVPR); \
-  if (nf > 1) \
-    require(p->supports_extension(EXT_ZVLSSEG)); \
 
 #define VI_CHECK_LOAD(elt_width) \
   VI_CHECK_STORE(elt_width); \
@@ -1753,29 +1748,87 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   } \
   p->VU.vstart = 0;
 
+#define VI_LD_WHOLE(elt_width) \
+  require_vector_novtype(true); \
+  const reg_t baseAddr = RS1; \
+  const reg_t vd = insn.rd(); \
+  const reg_t len = insn.v_nf() + 1; \
+  require_align(vd, len); \
+  const reg_t elt_per_reg = P.VU.vlenb / sizeof(elt_width ## _t); \
+  const reg_t size = len * elt_per_reg; \
+  if (P.VU.vstart < size) { \
+    reg_t i = P.VU.vstart / elt_per_reg; \
+    reg_t off = P.VU.vstart % elt_per_reg; \
+    if (off) { \
+      for (reg_t pos = off; pos < elt_per_reg; ++pos) { \
+        auto val = MMU.load_## elt_width(baseAddr + \
+          P.VU.vstart * sizeof(elt_width ## _t)); \
+        P.VU.elt<elt_width ## _t>(vd + i, pos, true) = val; \
+        P.VU.vstart++; \
+      } \
+      ++i; \
+    } \
+    for (; i < len; ++i) { \
+      for (reg_t pos = 0; pos < elt_per_reg; ++pos) { \
+        auto val = MMU.load_## elt_width(baseAddr + \
+          P.VU.vstart * sizeof(elt_width ## _t)); \
+        P.VU.elt<elt_width ## _t>(vd + i, pos, true) = val; \
+        P.VU.vstart++; \
+      } \
+    } \
+  } \
+  P.VU.vstart = 0; \
+
+#define VI_ST_WHOLE \
+  require_vector_novtype(true); \
+  const reg_t baseAddr = RS1; \
+  const reg_t vs3 = insn.rd(); \
+  const reg_t len = insn.v_nf() + 1; \
+  require_align(vs3, len); \
+  const reg_t size = len * P.VU.vlenb; \
+   \
+  if (P.VU.vstart < size) { \
+    reg_t i = P.VU.vstart / P.VU.vlenb; \
+    reg_t off = P.VU.vstart % P.VU.vlenb; \
+    if (off) { \
+      for (reg_t pos = off; pos < P.VU.vlenb; ++pos) { \
+        auto val = P.VU.elt<uint8_t>(vs3 + i, pos); \
+        MMU.store_uint8(baseAddr + P.VU.vstart, val); \
+        P.VU.vstart++; \
+      } \
+      i++; \
+    } \
+    for (; i < len; ++i) { \
+      for (reg_t pos = 0; pos < P.VU.vlenb; ++pos) { \
+        auto val = P.VU.elt<uint8_t>(vs3 + i, pos); \
+        MMU.store_uint8(baseAddr + P.VU.vstart, val); \
+        P.VU.vstart++; \
+      } \
+    } \
+  } \
+  P.VU.vstart = 0;
+
 //
 // vector: amo 
 //
 #define VI_AMO(op, type, idx_type) \
   require_vector; \
-  require_extension(EXT_ZVAMO); \
   require_align(insn.rd(), P.VU.vflmul); \
   require(P.VU.vsew <= P.get_xlen() && P.VU.vsew >= 32); \
   require_align(insn.rd(), P.VU.vflmul); \
-  P.VU.veew = idx_type; \
-  P.VU.vemul = ((float)P.VU.veew / P.VU.vsew * P.VU.vflmul); \
-  require(P.VU.vemul >= 0.125 && P.VU.vemul <= 8); \
-  require_align(insn.rs2(), P.VU.vemul); \
+  float vemul = ((float)idx_type / P.VU.vsew * P.VU.vflmul); \
+  require(vemul >= 0.125 && vemul <= 8); \
+  require_align(insn.rs2(), vemul); \
   if (insn.v_wd()) {\
     require_vm; \
-    if (P.VU.veew > P.VU.vsew) { \
+    if (idx_type > P.VU.vsew) { \
       if (insn.rd() != insn.rs2()) \
-        require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
-    } else if (P.VU.veew < P.VU.vsew) { \
-      if (P.VU.vemul < 1) {\
-        require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
+        require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \
+    } else if (idx_type < P.VU.vsew) { \
+      if (vemul < 1) {\
+        require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \
       } else {\
-        require_noover_widen(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vemul); \
+        require_noover_widen(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \
       } \
     } \
   } \
diff --git a/riscv/encoding.h b/riscv/encoding.h
index be66895..f8628c7 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -1092,10 +1092,46 @@
 #define MASK_VLE512FF_V  0x1df0707f
 #define MATCH_VLE1024FF_V 0x11007007
 #define MASK_VLE1024FF_V  0x1df0707f
-#define MATCH_VL1R_V 0x2800007
-#define MASK_VL1R_V  0xfff0707f
+#define MATCH_VL1RE8_V 0x2800007
+#define MASK_VL1RE8_V  0xfff0707f
+#define MATCH_VL1RE16_V 0x2805007
+#define MASK_VL1RE16_V  0xfff0707f
+#define MATCH_VL1RE32_V 0x2806007
+#define MASK_VL1RE32_V  0xfff0707f
+#define MATCH_VL1RE64_V 0x2807007
+#define MASK_VL1RE64_V  0xfff0707f
+#define MATCH_VL2RE8_V 0x22800007
+#define MASK_VL2RE8_V  0xfff0707f
+#define MATCH_VL2RE16_V 0x22805007
+#define MASK_VL2RE16_V  0xfff0707f
+#define MATCH_VL2RE32_V 0x22806007
+#define MASK_VL2RE32_V  0xfff0707f
+#define MATCH_VL2RE64_V 0x22807007
+#define MASK_VL2RE64_V  0xfff0707f
+#define MATCH_VL4RE8_V 0x62800007
+#define MASK_VL4RE8_V  0xfff0707f
+#define MATCH_VL4RE16_V 0x62805007
+#define MASK_VL4RE16_V  0xfff0707f
+#define MATCH_VL4RE32_V 0x62806007
+#define MASK_VL4RE32_V  0xfff0707f
+#define MATCH_VL4RE64_V 0x62807007
+#define MASK_VL4RE64_V  0xfff0707f
+#define MATCH_VL8RE8_V 0xe2800007
+#define MASK_VL8RE8_V  0xfff0707f
+#define MATCH_VL8RE16_V 0xe2805007
+#define MASK_VL8RE16_V  0xfff0707f
+#define MATCH_VL8RE32_V 0xe2806007
+#define MASK_VL8RE32_V  0xfff0707f
+#define MATCH_VL8RE64_V 0xe2807007
+#define MASK_VL8RE64_V  0xfff0707f
 #define MATCH_VS1R_V 0x2800027
 #define MASK_VS1R_V  0xfff0707f
+#define MATCH_VS2R_V 0x22800027
+#define MASK_VS2R_V  0xfff0707f
+#define MATCH_VS4R_V 0x62800027
+#define MASK_VS4R_V  0xfff0707f
+#define MATCH_VS8R_V 0xe2800027
+#define MASK_VS8R_V  0xfff0707f
 #define MATCH_VFADD_VF 0x5057
 #define MASK_VFADD_VF  0xfc00707f
 #define MATCH_VFSUB_VF 0x8005057
@@ -1406,6 +1442,8 @@
 #define MASK_VXOR_VV  0xfc00707f
 #define MATCH_VRGATHER_VV 0x30000057
 #define MASK_VRGATHER_VV  0xfc00707f
+#define MATCH_VRGATHEREI16_VV 0x38000057
+#define MASK_VRGATHEREI16_VV  0xfc00707f
 #define MATCH_VADC_VVM 0x40000057
 #define MASK_VADC_VVM  0xfe00707f
 #define MATCH_VMADC_VVM 0x44000057
@@ -1564,32 +1602,18 @@
 #define MASK_VASUB_VV  0xfc00707f
 #define MATCH_VMV_X_S 0x42002057
 #define MASK_VMV_X_S  0xfe0ff07f
-#define MATCH_VPOPC_M 0x40082057
-#define MASK_VPOPC_M  0xfc0ff07f
-#define MATCH_VFIRST_M 0x4008a057
-#define MASK_VFIRST_M  0xfc0ff07f
-#define MATCH_VZEXT_VF2 0x48032057
-#define MASK_VZEXT_VF2  0xfc0ff07f
-#define MATCH_VSEXT_VF2 0x4803a057
-#define MASK_VSEXT_VF2  0xfc0ff07f
-#define MATCH_VZEXT_VF4 0x48022057
-#define MASK_VZEXT_VF4  0xfc0ff07f
-#define MATCH_VSEXT_VF4 0x4802a057
-#define MASK_VSEXT_VF4  0xfc0ff07f
 #define MATCH_VZEXT_VF8 0x48012057
 #define MASK_VZEXT_VF8  0xfc0ff07f
 #define MATCH_VSEXT_VF8 0x4801a057
 #define MASK_VSEXT_VF8  0xfc0ff07f
-#define MATCH_VMSBF_M 0x5000a057
-#define MASK_VMSBF_M  0xfc0ff07f
-#define MATCH_VMSOF_M 0x50012057
-#define MASK_VMSOF_M  0xfc0ff07f
-#define MATCH_VMSIF_M 0x5001a057
-#define MASK_VMSIF_M  0xfc0ff07f
-#define MATCH_VIOTA_M 0x50082057
-#define MASK_VIOTA_M  0xfc0ff07f
-#define MATCH_VID_V 0x5008a057
-#define MASK_VID_V  0xfdfff07f
+#define MATCH_VZEXT_VF4 0x48022057
+#define MASK_VZEXT_VF4  0xfc0ff07f
+#define MATCH_VSEXT_VF4 0x4802a057
+#define MASK_VSEXT_VF4  0xfc0ff07f
+#define MATCH_VZEXT_VF2 0x48032057
+#define MASK_VZEXT_VF2  0xfc0ff07f
+#define MATCH_VSEXT_VF2 0x4803a057
+#define MASK_VSEXT_VF2  0xfc0ff07f
 #define MATCH_VCOMPRESS_VM 0x5e002057
 #define MASK_VCOMPRESS_VM  0xfe00707f
 #define MATCH_VMANDNOT_MM 0x60002057
@@ -1608,6 +1632,20 @@
 #define MASK_VMNOR_MM  0xfc00707f
 #define MATCH_VMXNOR_MM 0x7c002057
 #define MASK_VMXNOR_MM  0xfc00707f
+#define MATCH_VMSBF_M 0x5000a057
+#define MASK_VMSBF_M  0xfc0ff07f
+#define MATCH_VMSOF_M 0x50012057
+#define MASK_VMSOF_M  0xfc0ff07f
+#define MATCH_VMSIF_M 0x5001a057
+#define MASK_VMSIF_M  0xfc0ff07f
+#define MATCH_VIOTA_M 0x50082057
+#define MASK_VIOTA_M  0xfc0ff07f
+#define MATCH_VID_V 0x5008a057
+#define MASK_VID_V  0xfdfff07f
+#define MATCH_VPOPC_M 0x40082057
+#define MASK_VPOPC_M  0xfc0ff07f
+#define MATCH_VFIRST_M 0x4008a057
+#define MASK_VFIRST_M  0xfc0ff07f
 #define MATCH_VDIVU_VV 0x80002057
 #define MASK_VDIVU_VV  0xfc00707f
 #define MATCH_VDIV_VV 0x84002057
@@ -1668,12 +1706,12 @@
 #define MASK_VASUBU_VX  0xfc00707f
 #define MATCH_VASUB_VX 0x2c006057
 #define MASK_VASUB_VX  0xfc00707f
+#define MATCH_VMV_S_X 0x42006057
+#define MASK_VMV_S_X  0xfff0707f
 #define MATCH_VSLIDE1UP_VX 0x38006057
 #define MASK_VSLIDE1UP_VX  0xfc00707f
 #define MATCH_VSLIDE1DOWN_VX 0x3c006057
 #define MASK_VSLIDE1DOWN_VX  0xfc00707f
-#define MATCH_VMV_S_X 0x42006057
-#define MASK_VMV_S_X  0xfff0707f
 #define MATCH_VDIVU_VX 0x80006057
 #define MASK_VDIVU_VX  0xfc00707f
 #define MATCH_VDIV_VX 0x84006057
@@ -1728,80 +1766,88 @@
 #define MASK_VWMACCUS_VX  0xfc00707f
 #define MATCH_VWMACCSU_VX 0xfc006057
 #define MASK_VWMACCSU_VX  0xfc00707f
-#define MATCH_VAMOSWAPE8_V 0x800002f
-#define MASK_VAMOSWAPE8_V  0xf800707f
-#define MATCH_VAMOADDE8_V 0x2f
-#define MASK_VAMOADDE8_V  0xf800707f
-#define MATCH_VAMOXORE8_V 0x2000002f
-#define MASK_VAMOXORE8_V  0xf800707f
-#define MATCH_VAMOANDE8_V 0x6000002f
-#define MASK_VAMOANDE8_V  0xf800707f
-#define MATCH_VAMOORE8_V 0x4000002f
-#define MASK_VAMOORE8_V  0xf800707f
-#define MATCH_VAMOMINE8_V 0x8000002f
-#define MASK_VAMOMINE8_V  0xf800707f
-#define MATCH_VAMOMAXE8_V 0xa000002f
-#define MASK_VAMOMAXE8_V  0xf800707f
-#define MATCH_VAMOMINUE8_V 0xc000002f
-#define MASK_VAMOMINUE8_V  0xf800707f
-#define MATCH_VAMOMAXUE8_V 0xe000002f
-#define MASK_VAMOMAXUE8_V  0xf800707f
-#define MATCH_VAMOSWAPE16_V 0x800502f
-#define MASK_VAMOSWAPE16_V  0xf800707f
-#define MATCH_VAMOADDE16_V 0x502f
-#define MASK_VAMOADDE16_V  0xf800707f
-#define MATCH_VAMOXORE16_V 0x2000502f
-#define MASK_VAMOXORE16_V  0xf800707f
-#define MATCH_VAMOANDE16_V 0x6000502f
-#define MASK_VAMOANDE16_V  0xf800707f
-#define MATCH_VAMOORE16_V 0x4000502f
-#define MASK_VAMOORE16_V  0xf800707f
-#define MATCH_VAMOMINE16_V 0x8000502f
-#define MASK_VAMOMINE16_V  0xf800707f
-#define MATCH_VAMOMAXE16_V 0xa000502f
-#define MASK_VAMOMAXE16_V  0xf800707f
-#define MATCH_VAMOMINUE16_V 0xc000502f
-#define MASK_VAMOMINUE16_V  0xf800707f
-#define MATCH_VAMOMAXUE16_V 0xe000502f
-#define MASK_VAMOMAXUE16_V  0xf800707f
-#define MATCH_VAMOSWAPE32_V 0x800602f
-#define MASK_VAMOSWAPE32_V  0xf800707f
-#define MATCH_VAMOADDE32_V 0x602f
-#define MASK_VAMOADDE32_V  0xf800707f
-#define MATCH_VAMOXORE32_V 0x2000602f
-#define MASK_VAMOXORE32_V  0xf800707f
-#define MATCH_VAMOANDE32_V 0x6000602f
-#define MASK_VAMOANDE32_V  0xf800707f
-#define MATCH_VAMOORE32_V 0x4000602f
-#define MASK_VAMOORE32_V  0xf800707f
-#define MATCH_VAMOMINE32_V 0x8000602f
-#define MASK_VAMOMINE32_V  0xf800707f
-#define MATCH_VAMOMAXE32_V 0xa000602f
-#define MASK_VAMOMAXE32_V  0xf800707f
-#define MATCH_VAMOMINUE32_V 0xc000602f
-#define MASK_VAMOMINUE32_V  0xf800707f
-#define MATCH_VAMOMAXUE32_V 0xe000602f
-#define MASK_VAMOMAXUE32_V  0xf800707f
-#define MATCH_VAMOSWAPE64_V 0x800702f
-#define MASK_VAMOSWAPE64_V  0xf800707f
-#define MATCH_VAMOADDE64_V 0x702f
-#define MASK_VAMOADDE64_V  0xf800707f
-#define MATCH_VAMOXORE64_V 0x2000702f
-#define MASK_VAMOXORE64_V  0xf800707f
-#define MATCH_VAMOANDE64_V 0x6000702f
-#define MASK_VAMOANDE64_V  0xf800707f
-#define MATCH_VAMOORE64_V 0x4000702f
-#define MASK_VAMOORE64_V  0xf800707f
-#define MATCH_VAMOMINE64_V 0x8000702f
-#define MASK_VAMOMINE64_V  0xf800707f
-#define MATCH_VAMOMAXE64_V 0xa000702f
-#define MASK_VAMOMAXE64_V  0xf800707f
-#define MATCH_VAMOMINUE64_V 0xc000702f
-#define MASK_VAMOMINUE64_V  0xf800707f
-#define MATCH_VAMOMAXUE64_V 0xe000702f
-#define MASK_VAMOMAXUE64_V  0xf800707f
+#define MATCH_VAMOSWAPEI8_V 0x800002f
+#define MASK_VAMOSWAPEI8_V  0xf800707f
+#define MATCH_VAMOADDEI8_V 0x2f
+#define MASK_VAMOADDEI8_V  0xf800707f
+#define MATCH_VAMOXOREI8_V 0x2000002f
+#define MASK_VAMOXOREI8_V  0xf800707f
+#define MATCH_VAMOANDEI8_V 0x6000002f
+#define MASK_VAMOANDEI8_V  0xf800707f
+#define MATCH_VAMOOREI8_V 0x4000002f
+#define MASK_VAMOOREI8_V  0xf800707f
+#define MATCH_VAMOMINEI8_V 0x8000002f
+#define MASK_VAMOMINEI8_V  0xf800707f
+#define MATCH_VAMOMAXEI8_V 0xa000002f
+#define MASK_VAMOMAXEI8_V  0xf800707f
+#define MATCH_VAMOMINUEI8_V 0xc000002f
+#define MASK_VAMOMINUEI8_V  0xf800707f
+#define MATCH_VAMOMAXUEI8_V 0xe000002f
+#define MASK_VAMOMAXUEI8_V  0xf800707f
+#define MATCH_VAMOSWAPEI16_V 0x800502f
+#define MASK_VAMOSWAPEI16_V  0xf800707f
+#define MATCH_VAMOADDEI16_V 0x502f
+#define MASK_VAMOADDEI16_V  0xf800707f
+#define MATCH_VAMOXOREI16_V 0x2000502f
+#define MASK_VAMOXOREI16_V  0xf800707f
+#define MATCH_VAMOANDEI16_V 0x6000502f
+#define MASK_VAMOANDEI16_V  0xf800707f
+#define MATCH_VAMOOREI16_V 0x4000502f
+#define MASK_VAMOOREI16_V  0xf800707f
+#define MATCH_VAMOMINEI16_V 0x8000502f
+#define MASK_VAMOMINEI16_V  0xf800707f
+#define MATCH_VAMOMAXEI16_V 0xa000502f
+#define MASK_VAMOMAXEI16_V  0xf800707f
+#define MATCH_VAMOMINUEI16_V 0xc000502f
+#define MASK_VAMOMINUEI16_V  0xf800707f
+#define MATCH_VAMOMAXUEI16_V 0xe000502f
+#define MASK_VAMOMAXUEI16_V  0xf800707f
+#define MATCH_VAMOSWAPEI32_V 0x800602f
+#define MASK_VAMOSWAPEI32_V  0xf800707f
+#define MATCH_VAMOADDEI32_V 0x602f
+#define MASK_VAMOADDEI32_V  0xf800707f
+#define MATCH_VAMOXOREI32_V 0x2000602f
+#define MASK_VAMOXOREI32_V  0xf800707f
+#define MATCH_VAMOANDEI32_V 0x6000602f
+#define MASK_VAMOANDEI32_V  0xf800707f
+#define MATCH_VAMOOREI32_V 0x4000602f
+#define MASK_VAMOOREI32_V  0xf800707f
+#define MATCH_VAMOMINEI32_V 0x8000602f
+#define MASK_VAMOMINEI32_V  0xf800707f
+#define MATCH_VAMOMAXEI32_V 0xa000602f
+#define MASK_VAMOMAXEI32_V  0xf800707f
+#define MATCH_VAMOMINUEI32_V 0xc000602f
+#define MASK_VAMOMINUEI32_V  0xf800707f
+#define MATCH_VAMOMAXUEI32_V 0xe000602f
+#define MASK_VAMOMAXUEI32_V  0xf800707f
+#define MATCH_VAMOSWAPEI64_V 0x800702f
+#define MASK_VAMOSWAPEI64_V  0xf800707f
+#define MATCH_VAMOADDEI64_V 0x702f
+#define MASK_VAMOADDEI64_V  0xf800707f
+#define MATCH_VAMOXOREI64_V 0x2000702f
+#define MASK_VAMOXOREI64_V  0xf800707f
+#define MATCH_VAMOANDEI64_V 0x6000702f
+#define MASK_VAMOANDEI64_V  0xf800707f
+#define MATCH_VAMOOREI64_V 0x4000702f
+#define MASK_VAMOOREI64_V  0xf800707f
+#define MATCH_VAMOMINEI64_V 0x8000702f
+#define MASK_VAMOMINEI64_V  0xf800707f
+#define MATCH_VAMOMAXEI64_V 0xa000702f
+#define MASK_VAMOMAXEI64_V  0xf800707f
+#define MATCH_VAMOMINUEI64_V 0xc000702f
+#define MASK_VAMOMINUEI64_V  0xf800707f
+#define MATCH_VAMOMAXUEI64_V 0xe000702f
+#define MASK_VAMOMAXUEI64_V  0xf800707f
 #define MATCH_VMVNFR_V 0x9e003057
 #define MASK_VMVNFR_V  0xfe00707f
+#define MATCH_VL1R_V 0x2800007
+#define MASK_VL1R_V  0xfff0707f
+#define MATCH_VL2R_V 0x2805007
+#define MASK_VL2R_V  0xfff0707f
+#define MATCH_VL4R_V 0x2806007
+#define MASK_VL4R_V  0xfff0707f
+#define MATCH_VL8R_V 0x2807007
+#define MASK_VL8R_V  0xfff0707f
 #define CSR_FFLAGS 0x1
 #define CSR_FRM 0x2
 #define CSR_FCSR 0x3
@@ -2503,8 +2549,26 @@ DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V)
 DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V)
 DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V)
 DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V)
-DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V)
+DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V)
+DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V)
+DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V)
+DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V)
+DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V)
+DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V)
+DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V)
+DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V)
+DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V)
+DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V)
+DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V)
+DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V)
+DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V)
+DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V)
+DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V)
+DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V)
 DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V)
+DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V)
+DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V)
+DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V)
 DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF)
 DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF)
 DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF)
@@ -2660,6 +2724,7 @@ DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV)
 DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV)
 DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV)
 DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV)
+DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV)
 DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM)
 DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM)
 DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM)
@@ -2739,19 +2804,12 @@ DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV)
 DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV)
 DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV)
 DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S)
-DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
-DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
-DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2)
-DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2)
-DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4)
-DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4)
 DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8)
 DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8)
-DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
-DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
-DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
-DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
-DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
+DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4)
+DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4)
+DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2)
+DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2)
 DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM)
 DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM)
 DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM)
@@ -2761,6 +2819,13 @@ DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM)
 DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM)
 DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM)
 DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM)
+DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
+DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
+DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
+DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
+DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
+DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
+DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
 DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
 DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
 DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV)
@@ -2791,9 +2856,9 @@ DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX)
 DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX)
 DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX)
 DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX)
+DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X)
 DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX)
 DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX)
-DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X)
 DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX)
 DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX)
 DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX)
@@ -2821,43 +2886,47 @@ DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX)
 DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX)
 DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX)
 DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX)
-DECLARE_INSN(vamoswape8_v, MATCH_VAMOSWAPE8_V, MASK_VAMOSWAPE8_V)
-DECLARE_INSN(vamoadde8_v, MATCH_VAMOADDE8_V, MASK_VAMOADDE8_V)
-DECLARE_INSN(vamoxore8_v, MATCH_VAMOXORE8_V, MASK_VAMOXORE8_V)
-DECLARE_INSN(vamoande8_v, MATCH_VAMOANDE8_V, MASK_VAMOANDE8_V)
-DECLARE_INSN(vamoore8_v, MATCH_VAMOORE8_V, MASK_VAMOORE8_V)
-DECLARE_INSN(vamomine8_v, MATCH_VAMOMINE8_V, MASK_VAMOMINE8_V)
-DECLARE_INSN(vamomaxe8_v, MATCH_VAMOMAXE8_V, MASK_VAMOMAXE8_V)
-DECLARE_INSN(vamominue8_v, MATCH_VAMOMINUE8_V, MASK_VAMOMINUE8_V)
-DECLARE_INSN(vamomaxue8_v, MATCH_VAMOMAXUE8_V, MASK_VAMOMAXUE8_V)
-DECLARE_INSN(vamoswape16_v, MATCH_VAMOSWAPE16_V, MASK_VAMOSWAPE16_V)
-DECLARE_INSN(vamoadde16_v, MATCH_VAMOADDE16_V, MASK_VAMOADDE16_V)
-DECLARE_INSN(vamoxore16_v, MATCH_VAMOXORE16_V, MASK_VAMOXORE16_V)
-DECLARE_INSN(vamoande16_v, MATCH_VAMOANDE16_V, MASK_VAMOANDE16_V)
-DECLARE_INSN(vamoore16_v, MATCH_VAMOORE16_V, MASK_VAMOORE16_V)
-DECLARE_INSN(vamomine16_v, MATCH_VAMOMINE16_V, MASK_VAMOMINE16_V)
-DECLARE_INSN(vamomaxe16_v, MATCH_VAMOMAXE16_V, MASK_VAMOMAXE16_V)
-DECLARE_INSN(vamominue16_v, MATCH_VAMOMINUE16_V, MASK_VAMOMINUE16_V)
-DECLARE_INSN(vamomaxue16_v, MATCH_VAMOMAXUE16_V, MASK_VAMOMAXUE16_V)
-DECLARE_INSN(vamoswape32_v, MATCH_VAMOSWAPE32_V, MASK_VAMOSWAPE32_V)
-DECLARE_INSN(vamoadde32_v, MATCH_VAMOADDE32_V, MASK_VAMOADDE32_V)
-DECLARE_INSN(vamoxore32_v, MATCH_VAMOXORE32_V, MASK_VAMOXORE32_V)
-DECLARE_INSN(vamoande32_v, MATCH_VAMOANDE32_V, MASK_VAMOANDE32_V)
-DECLARE_INSN(vamoore32_v, MATCH_VAMOORE32_V, MASK_VAMOORE32_V)
-DECLARE_INSN(vamomine32_v, MATCH_VAMOMINE32_V, MASK_VAMOMINE32_V)
-DECLARE_INSN(vamomaxe32_v, MATCH_VAMOMAXE32_V, MASK_VAMOMAXE32_V)
-DECLARE_INSN(vamominue32_v, MATCH_VAMOMINUE32_V, MASK_VAMOMINUE32_V)
-DECLARE_INSN(vamomaxue32_v, MATCH_VAMOMAXUE32_V, MASK_VAMOMAXUE32_V)
-DECLARE_INSN(vamoswape64_v, MATCH_VAMOSWAPE64_V, MASK_VAMOSWAPE64_V)
-DECLARE_INSN(vamoadde64_v, MATCH_VAMOADDE64_V, MASK_VAMOADDE64_V)
-DECLARE_INSN(vamoxore64_v, MATCH_VAMOXORE64_V, MASK_VAMOXORE64_V)
-DECLARE_INSN(vamoande64_v, MATCH_VAMOANDE64_V, MASK_VAMOANDE64_V)
-DECLARE_INSN(vamoore64_v, MATCH_VAMOORE64_V, MASK_VAMOORE64_V)
-DECLARE_INSN(vamomine64_v, MATCH_VAMOMINE64_V, MASK_VAMOMINE64_V)
-DECLARE_INSN(vamomaxe64_v, MATCH_VAMOMAXE64_V, MASK_VAMOMAXE64_V)
-DECLARE_INSN(vamominue64_v, MATCH_VAMOMINUE64_V, MASK_VAMOMINUE64_V)
-DECLARE_INSN(vamomaxue64_v, MATCH_VAMOMAXUE64_V, MASK_VAMOMAXUE64_V)
+DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V)
+DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V)
+DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V)
+DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V)
+DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V)
+DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V)
+DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V)
+DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V)
+DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V)
+DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V)
+DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V)
+DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V)
+DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V)
+DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V)
+DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V)
+DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V)
+DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V)
+DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V)
+DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V)
+DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V)
+DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V)
+DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V)
+DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V)
+DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V)
+DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V)
+DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V)
+DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V)
+DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V)
+DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V)
+DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V)
+DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V)
+DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V)
+DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V)
+DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V)
+DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V)
+DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V)
 DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V)
+DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V)
+DECLARE_INSN(vl2r_v, MATCH_VL2R_V, MASK_VL2R_V)
+DECLARE_INSN(vl4r_v, MATCH_VL4R_V, MASK_VL4R_V)
+DECLARE_INSN(vl8r_v, MATCH_VL8R_V, MASK_VL8R_V)
 #endif
 #ifdef DECLARE_CSR
 DECLARE_CSR(fflags, CSR_FFLAGS)
diff --git a/riscv/insns/vamoadde16_v.h b/riscv/insns/vamoaddei16_v.h
index 3cb3db7..3cb3db7 100644
--- a/riscv/insns/vamoadde16_v.h
+++ b/riscv/insns/vamoaddei16_v.h
diff --git a/riscv/insns/vamoadde32_v.h b/riscv/insns/vamoaddei32_v.h
index 2bd77fc..2bd77fc 100644
--- a/riscv/insns/vamoadde32_v.h
+++ b/riscv/insns/vamoaddei32_v.h
diff --git a/riscv/insns/vamoadde64_v.h b/riscv/insns/vamoaddei64_v.h
index 79ca748..79ca748 100644
--- a/riscv/insns/vamoadde64_v.h
+++ b/riscv/insns/vamoaddei64_v.h
diff --git a/riscv/insns/vamoadde8_v.h b/riscv/insns/vamoaddei8_v.h
index 06b8c79..06b8c79 100644
--- a/riscv/insns/vamoadde8_v.h
+++ b/riscv/insns/vamoaddei8_v.h
diff --git a/riscv/insns/vamoande16_v.h b/riscv/insns/vamoandei16_v.h
index be11949..be11949 100644
--- a/riscv/insns/vamoande16_v.h
+++ b/riscv/insns/vamoandei16_v.h
diff --git a/riscv/insns/vamoande32_v.h b/riscv/insns/vamoandei32_v.h
index 7150670..7150670 100644
--- a/riscv/insns/vamoande32_v.h
+++ b/riscv/insns/vamoandei32_v.h
diff --git a/riscv/insns/vamoande64_v.h b/riscv/insns/vamoandei64_v.h
index 3efae3b..3efae3b 100644
--- a/riscv/insns/vamoande64_v.h
+++ b/riscv/insns/vamoandei64_v.h
diff --git a/riscv/insns/vamoande8_v.h b/riscv/insns/vamoandei8_v.h
index c47645d..c47645d 100644
--- a/riscv/insns/vamoande8_v.h
+++ b/riscv/insns/vamoandei8_v.h
diff --git a/riscv/insns/vamomaxe16_v.h b/riscv/insns/vamomaxei16_v.h
index ca67893..ca67893 100644
--- a/riscv/insns/vamomaxe16_v.h
+++ b/riscv/insns/vamomaxei16_v.h
diff --git a/riscv/insns/vamomaxe32_v.h b/riscv/insns/vamomaxei32_v.h
index b6823cd..b6823cd 100644
--- a/riscv/insns/vamomaxe32_v.h
+++ b/riscv/insns/vamomaxei32_v.h
diff --git a/riscv/insns/vamomaxe64_v.h b/riscv/insns/vamomaxei64_v.h
index 46e8a3b..46e8a3b 100644
--- a/riscv/insns/vamomaxe64_v.h
+++ b/riscv/insns/vamomaxei64_v.h
diff --git a/riscv/insns/vamomaxe8_v.h b/riscv/insns/vamomaxei8_v.h
index 9697b3a..9697b3a 100644
--- a/riscv/insns/vamomaxe8_v.h
+++ b/riscv/insns/vamomaxei8_v.h
diff --git a/riscv/insns/vamomaxue16_v.h b/riscv/insns/vamomaxuei16_v.h
index e05971d..e05971d 100644
--- a/riscv/insns/vamomaxue16_v.h
+++ b/riscv/insns/vamomaxuei16_v.h
diff --git a/riscv/insns/vamomaxue32_v.h b/riscv/insns/vamomaxuei32_v.h
index 9b87354..9b87354 100644
--- a/riscv/insns/vamomaxue32_v.h
+++ b/riscv/insns/vamomaxuei32_v.h
diff --git a/riscv/insns/vamomaxue64_v.h b/riscv/insns/vamomaxuei64_v.h
index bbfbc9f..bbfbc9f 100644
--- a/riscv/insns/vamomaxue64_v.h
+++ b/riscv/insns/vamomaxuei64_v.h
diff --git a/riscv/insns/vamomaxue8_v.h b/riscv/insns/vamomaxuei8_v.h
index 357ba24..357ba24 100644
--- a/riscv/insns/vamomaxue8_v.h
+++ b/riscv/insns/vamomaxuei8_v.h
diff --git a/riscv/insns/vamomine16_v.h b/riscv/insns/vamominei16_v.h
index 9d1ecac..9d1ecac 100644
--- a/riscv/insns/vamomine16_v.h
+++ b/riscv/insns/vamominei16_v.h
diff --git a/riscv/insns/vamomine32_v.h b/riscv/insns/vamominei32_v.h
index 6cb8475..6cb8475 100644
--- a/riscv/insns/vamomine32_v.h
+++ b/riscv/insns/vamominei32_v.h
diff --git a/riscv/insns/vamomine64_v.h b/riscv/insns/vamominei64_v.h
index 9ef3d4e..9ef3d4e 100644
--- a/riscv/insns/vamomine64_v.h
+++ b/riscv/insns/vamominei64_v.h
diff --git a/riscv/insns/vamomine8_v.h b/riscv/insns/vamominei8_v.h
index 5c035ea..5c035ea 100644
--- a/riscv/insns/vamomine8_v.h
+++ b/riscv/insns/vamominei8_v.h
diff --git a/riscv/insns/vamominue16_v.h b/riscv/insns/vamominuei16_v.h
index d4a8f89..d4a8f89 100644
--- a/riscv/insns/vamominue16_v.h
+++ b/riscv/insns/vamominuei16_v.h
diff --git a/riscv/insns/vamominue32_v.h b/riscv/insns/vamominuei32_v.h
index 16296c5..16296c5 100644
--- a/riscv/insns/vamominue32_v.h
+++ b/riscv/insns/vamominuei32_v.h
diff --git a/riscv/insns/vamominue64_v.h b/riscv/insns/vamominuei64_v.h
index fd850fd..fd850fd 100644
--- a/riscv/insns/vamominue64_v.h
+++ b/riscv/insns/vamominuei64_v.h
diff --git a/riscv/insns/vamominue8_v.h b/riscv/insns/vamominuei8_v.h
index 3749d05..3749d05 100644
--- a/riscv/insns/vamominue8_v.h
+++ b/riscv/insns/vamominuei8_v.h
diff --git a/riscv/insns/vamoore16_v.h b/riscv/insns/vamoorei16_v.h
index a5ba1ca..a5ba1ca 100644
--- a/riscv/insns/vamoore16_v.h
+++ b/riscv/insns/vamoorei16_v.h
diff --git a/riscv/insns/vamoore32_v.h b/riscv/insns/vamoorei32_v.h
index 94e4458..94e4458 100644
--- a/riscv/insns/vamoore32_v.h
+++ b/riscv/insns/vamoorei32_v.h
diff --git a/riscv/insns/vamoore64_v.h b/riscv/insns/vamoorei64_v.h
index 84e0394..84e0394 100644
--- a/riscv/insns/vamoore64_v.h
+++ b/riscv/insns/vamoorei64_v.h
diff --git a/riscv/insns/vamoore8_v.h b/riscv/insns/vamoorei8_v.h
index 364035d..364035d 100644
--- a/riscv/insns/vamoore8_v.h
+++ b/riscv/insns/vamoorei8_v.h
diff --git a/riscv/insns/vamoswape16_v.h b/riscv/insns/vamoswapei16_v.h
index 31ff021..31ff021 100644
--- a/riscv/insns/vamoswape16_v.h
+++ b/riscv/insns/vamoswapei16_v.h
diff --git a/riscv/insns/vamoswape32_v.h b/riscv/insns/vamoswapei32_v.h
index a574192..a574192 100644
--- a/riscv/insns/vamoswape32_v.h
+++ b/riscv/insns/vamoswapei32_v.h
diff --git a/riscv/insns/vamoswape64_v.h b/riscv/insns/vamoswapei64_v.h
index 58bd035..58bd035 100644
--- a/riscv/insns/vamoswape64_v.h
+++ b/riscv/insns/vamoswapei64_v.h
diff --git a/riscv/insns/vamoswape8_v.h b/riscv/insns/vamoswapei8_v.h
index af37c8c..af37c8c 100644
--- a/riscv/insns/vamoswape8_v.h
+++ b/riscv/insns/vamoswapei8_v.h
diff --git a/riscv/insns/vamoxore16_v.h b/riscv/insns/vamoxorei16_v.h
index 61e8c32..61e8c32 100644
--- a/riscv/insns/vamoxore16_v.h
+++ b/riscv/insns/vamoxorei16_v.h
diff --git a/riscv/insns/vamoxore32_v.h b/riscv/insns/vamoxorei32_v.h
index d48d951..d48d951 100644
--- a/riscv/insns/vamoxore32_v.h
+++ b/riscv/insns/vamoxorei32_v.h
diff --git a/riscv/insns/vamoxore64_v.h b/riscv/insns/vamoxorei64_v.h
index f7a3ca4..f7a3ca4 100644
--- a/riscv/insns/vamoxore64_v.h
+++ b/riscv/insns/vamoxorei64_v.h
diff --git a/riscv/insns/vamoxore8_v.h b/riscv/insns/vamoxorei8_v.h
index 4b6c798..4b6c798 100644
--- a/riscv/insns/vamoxore8_v.h
+++ b/riscv/insns/vamoxorei8_v.h
diff --git a/riscv/insns/vl1r_v.h b/riscv/insns/vl1r_v.h
deleted file mode 100644
index 9289634..0000000
--- a/riscv/insns/vl1r_v.h
+++ /dev/null
@@ -1,9 +0,0 @@
-// vl1r.v vd, (rs1)
-require_vector_novtype(true);
-const reg_t baseAddr = RS1;
-const reg_t vd = insn.rd();
-for (reg_t i = P.VU.vstart; i < P.VU.vlenb; ++i) {
-  auto val = MMU.load_uint8(baseAddr + i);
-  P.VU.elt<uint8_t>(vd, i, true) = val;
-}
-P.VU.vstart = 0;
diff --git a/riscv/insns/vl1re16_v.h b/riscv/insns/vl1re16_v.h
new file mode 100644
index 0000000..220e83e
--- /dev/null
+++ b/riscv/insns/vl1re16_v.h
@@ -0,0 +1,2 @@
+// vl1re16.v vd, (rs1)
+VI_LD_WHOLE(uint16);
diff --git a/riscv/insns/vl1re32_v.h b/riscv/insns/vl1re32_v.h
new file mode 100644
index 0000000..e72ca02
--- /dev/null
+++ b/riscv/insns/vl1re32_v.h
@@ -0,0 +1,2 @@
+// vl1re32.v vd, (rs1)
+VI_LD_WHOLE(uint32);
diff --git a/riscv/insns/vl1re64_v.h b/riscv/insns/vl1re64_v.h
new file mode 100644
index 0000000..265701a
--- /dev/null
+++ b/riscv/insns/vl1re64_v.h
@@ -0,0 +1,2 @@
+// vl1re64.v vd, (rs1)
+VI_LD_WHOLE(uint64);
diff --git a/riscv/insns/vl1re8_v.h b/riscv/insns/vl1re8_v.h
new file mode 100644
index 0000000..b4ce661
--- /dev/null
+++ b/riscv/insns/vl1re8_v.h
@@ -0,0 +1,2 @@
+// vl1re8.v vd, (rs1)
+VI_LD_WHOLE(uint8);
diff --git a/riscv/insns/vl2re16_v.h b/riscv/insns/vl2re16_v.h
new file mode 100644
index 0000000..2846edd
--- /dev/null
+++ b/riscv/insns/vl2re16_v.h
@@ -0,0 +1,2 @@
+// vl2e16.v vd, (rs1)
+VI_LD_WHOLE(uint16);
diff --git a/riscv/insns/vl2re32_v.h b/riscv/insns/vl2re32_v.h
new file mode 100644
index 0000000..5cea835
--- /dev/null
+++ b/riscv/insns/vl2re32_v.h
@@ -0,0 +1,2 @@
+// vl2re32.v vd, (rs1)
+VI_LD_WHOLE(uint32);
diff --git a/riscv/insns/vl2re64_v.h b/riscv/insns/vl2re64_v.h
new file mode 100644
index 0000000..efdf2ce
--- /dev/null
+++ b/riscv/insns/vl2re64_v.h
@@ -0,0 +1,2 @@
+// vl2re64.v vd, (rs1)
+VI_LD_WHOLE(uint64);
diff --git a/riscv/insns/vl2re8_v.h b/riscv/insns/vl2re8_v.h
new file mode 100644
index 0000000..fcc3c4c
--- /dev/null
+++ b/riscv/insns/vl2re8_v.h
@@ -0,0 +1,2 @@
+// vl2re8.v vd, (rs1)
+VI_LD_WHOLE(uint8);
diff --git a/riscv/insns/vl4re16_v.h b/riscv/insns/vl4re16_v.h
new file mode 100644
index 0000000..0363418
--- /dev/null
+++ b/riscv/insns/vl4re16_v.h
@@ -0,0 +1,2 @@
+// vl4re16.v vd, (rs1)
+VI_LD_WHOLE(uint16);
diff --git a/riscv/insns/vl4re32_v.h b/riscv/insns/vl4re32_v.h
new file mode 100644
index 0000000..e37cc1a
--- /dev/null
+++ b/riscv/insns/vl4re32_v.h
@@ -0,0 +1,2 @@
+// vl4re32.v vd, (rs1)
+VI_LD_WHOLE(uint32);
diff --git a/riscv/insns/vl4re64_v.h b/riscv/insns/vl4re64_v.h
new file mode 100644
index 0000000..11486f5
--- /dev/null
+++ b/riscv/insns/vl4re64_v.h
@@ -0,0 +1,2 @@
+// vl4re64.v vd, (rs1)
+VI_LD_WHOLE(uint64);
diff --git a/riscv/insns/vl4re8_v.h b/riscv/insns/vl4re8_v.h
new file mode 100644
index 0000000..f9ce3ff
--- /dev/null
+++ b/riscv/insns/vl4re8_v.h
@@ -0,0 +1,2 @@
+// vl4re8.v vd, (rs1)
+VI_LD_WHOLE(uint8);
diff --git a/riscv/insns/vl8re16_v.h b/riscv/insns/vl8re16_v.h
new file mode 100644
index 0000000..0b3f141
--- /dev/null
+++ b/riscv/insns/vl8re16_v.h
@@ -0,0 +1,2 @@
+// vl8re16.v vd, (rs1)
+VI_LD_WHOLE(uint16);
diff --git a/riscv/insns/vl8re32_v.h b/riscv/insns/vl8re32_v.h
new file mode 100644
index 0000000..3372b89
--- /dev/null
+++ b/riscv/insns/vl8re32_v.h
@@ -0,0 +1,2 @@
+// vl8re32.v vd, (rs1)
+VI_LD_WHOLE(uint32);
diff --git a/riscv/insns/vl8re64_v.h b/riscv/insns/vl8re64_v.h
new file mode 100644
index 0000000..f9a9ca9
--- /dev/null
+++ b/riscv/insns/vl8re64_v.h
@@ -0,0 +1,2 @@
+// vl8re64.v vd, (rs1)
+VI_LD_WHOLE(uint64);
diff --git a/riscv/insns/vl8re8_v.h b/riscv/insns/vl8re8_v.h
new file mode 100644
index 0000000..ee05e81
--- /dev/null
+++ b/riscv/insns/vl8re8_v.h
@@ -0,0 +1,2 @@
+// vl8re8.v vd, (rs1)
+VI_LD_WHOLE(uint8);
diff --git a/riscv/insns/vrgatherei16_vv.h b/riscv/insns/vrgatherei16_vv.h
new file mode 100644
index 0000000..780b0ee
--- /dev/null
+++ b/riscv/insns/vrgatherei16_vv.h
@@ -0,0 +1,33 @@
+// vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]];
+float vemul = (16.0 / P.VU.vsew * P.VU.vflmul);
+require(vemul >= 0.125 && vemul <= 8);
+require_align(insn.rd(), P.VU.vflmul);
+require_align(insn.rs2(), P.VU.vflmul);
+require_align(insn.rs1(), vemul);
+require(insn.rd() != insn.rs2() && insn.rd() != insn.rs1());
+require_vm;
+
+VI_LOOP_BASE
+  switch (sew) {
+  case e8: {
+    auto vs1 = P.VU.elt<uint16_t>(rs1_num, i);
+    P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1);
+    break;
+  }
+  case e16: {
+    auto vs1 = P.VU.elt<uint16_t>(rs1_num, i);
+    P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1);
+    break;
+  }
+  case e32: {
+    auto vs1 = P.VU.elt<uint16_t>(rs1_num, i);
+    P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1);
+    break;
+  }
+  default: {
+    auto vs1 = P.VU.elt<uint16_t>(rs1_num, i);
+    P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1);
+    break;
+  }
+  }
+VI_LOOP_END;
diff --git a/riscv/insns/vs1r_v.h b/riscv/insns/vs1r_v.h
index 5ccbd5f..1932ec0 100644
--- a/riscv/insns/vs1r_v.h
+++ b/riscv/insns/vs1r_v.h
@@ -1,9 +1,2 @@
 // vs1r.v vs3, (rs1)
-require_vector_novtype(true);
-const reg_t baseAddr = RS1;
-const reg_t vs3 = insn.rd();
-for (reg_t i = P.VU.vstart; i < P.VU.vlenb; ++i) {
-  auto val = P.VU.elt<uint8_t>(vs3, i);
-  MMU.store_uint8(baseAddr + i, val);
-}
-P.VU.vstart = 0;
+VI_ST_WHOLE
diff --git a/riscv/insns/vs2r_v.h b/riscv/insns/vs2r_v.h
new file mode 100644
index 0000000..2e515b4
--- /dev/null
+++ b/riscv/insns/vs2r_v.h
@@ -0,0 +1,2 @@
+// vs2r.v vs3, (rs1)
+VI_ST_WHOLE
diff --git a/riscv/insns/vs4r_v.h b/riscv/insns/vs4r_v.h
new file mode 100644
index 0000000..161bf89
--- /dev/null
+++ b/riscv/insns/vs4r_v.h
@@ -0,0 +1,2 @@
+// vs4r.v vs3, (rs1)
+VI_ST_WHOLE
diff --git a/riscv/insns/vs8r_v.h b/riscv/insns/vs8r_v.h
new file mode 100644
index 0000000..1ad2575
--- /dev/null
+++ b/riscv/insns/vs8r_v.h
@@ -0,0 +1,2 @@
+// vs8r.v vs3, (rs1)
+VI_ST_WHOLE
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 798c1c2..50092c8 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -142,13 +142,12 @@ void processor_t::parse_varch_string(const char* s)
     bad_varch_string(s, "The integer value should be the power of 2");
   }
 
+  if (slen == 0)
+    slen = vlen;
+
   /* Vector spec requirements. */
   if (vlen < elen)
     bad_varch_string(s, "vlen must be >= elen");
-  if (vlen < slen)
-    bad_varch_string(s, "vlen must be >= slen");
-  if (slen < 32)
-    bad_varch_string(s, "slen must be >= 32");
   if ((unsigned) elen < std::max(max_xlen, get_flen()))
     bad_varch_string(s, "elen must be >= max(xlen, flen)");
   if (vlen != slen)
@@ -160,7 +159,6 @@ void processor_t::parse_varch_string(const char* s)
 
   VU.VLEN = vlen;
   VU.ELEN = elen;
-  VU.SLEN = slen;
   VU.vlenb = vlen / 8;
 }
 
@@ -262,10 +260,6 @@ void processor_t::parse_isa_string(const char* str)
       auto ext_str = std::string(ext, end - ext);
       if (ext_str == "zfh") {
         extension_table[EXT_ZFH] = true;
-      } else if (ext_str == "zvamo") {
-        extension_table[EXT_ZVAMO] = true;
-      } else if (ext_str == "zvlsseg") {
-        extension_table[EXT_ZVLSSEG] = true;
       } else if (ext_str == "zvqmac") {
         extension_table[EXT_ZVQMAC] = true;
       } else {
@@ -294,13 +288,6 @@ void processor_t::parse_isa_string(const char* str)
   if (supports_extension('Q') && !supports_extension('D'))
     bad_isa_string(str, "'Q' extension requires 'D'");
 
-  if (supports_extension(EXT_ZVAMO) &&
-      !(supports_extension('A') && supports_extension('V')))
-    bad_isa_string(str, "'Zvamo' extension requires 'A' and 'V'");
-
-  if (supports_extension(EXT_ZVLSSEG) && !supports_extension('V'))
-    bad_isa_string(str, "'Zvlsseg' extension requires 'V'");
-
   if (supports_extension(EXT_ZVQMAC) && !supports_extension('V'))
     bad_isa_string(str, "'Zvqmac' extension requires 'V'");
 }
@@ -385,8 +372,8 @@ void processor_t::vectorUnit_t::reset(){
   free(reg_file);
   VLEN = get_vlen();
   ELEN = get_elen();
-  SLEN = get_slen(); // registers are simply concatenated
-  reg_file = malloc(NVPR * (VLEN/8));
+  reg_file = malloc(NVPR * vlenb);
+  memset(reg_file, 0, NVPR * vlenb);
 
   vtype = 0;
   set_vl(0, 0, 0, -1); // default to illegal configuration
@@ -400,8 +387,6 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
     new_vlmul = int8_t(BITS(newType, 2, 0) << 5) >> 5;
     vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul);
     vlmax = (VLEN/vsew) * vflmul;
-    vemul = vflmul;
-    veew = vsew;
     vta = BITS(newType, 6, 6);
     vma = BITS(newType, 7, 7);
     vediv = 1 << BITS(newType, 9, 8);
diff --git a/riscv/processor.h b/riscv/processor.h
index d8f3c79..6c16eb9 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -246,9 +246,7 @@ typedef enum {
 typedef enum {
   // 65('A') ~ 90('Z') is reserved for standard isa in misa
   EXT_ZFH   = 0,
-  EXT_ZVAMO,
   EXT_ZVEDIV,
-  EXT_ZVLSSEG,
   EXT_ZVQMAC,
 } isa_extension_t;
 
@@ -476,11 +474,8 @@ public:
       reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
       reg_t vma, vta;
       reg_t vediv, vsew;
-      reg_t veew;
-      float vemul;
       float vflmul;
-      reg_t vmel;
-      reg_t ELEN, VLEN, SLEN;
+      reg_t ELEN, VLEN;
       bool vill;
 
       // vector element for varies SEW
@@ -523,7 +518,7 @@ public:
 
       reg_t get_vlen() { return VLEN; }
       reg_t get_elen() { return ELEN; }
-      reg_t get_slen() { return SLEN; }
+      reg_t get_slen() { return VLEN; }
 
       VRM get_vround_mode() {
         return (VRM)vxrm;
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 73c4cef..6a86158 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -472,6 +472,7 @@ riscv_insn_ext_v_alu_int = \
 	vrgather_vi \
 	vrgather_vv \
 	vrgather_vx \
+	vrgatherei16_vv \
 	vrsub_vi \
 	vrsub_vx \
 	vsadd_vi \
@@ -655,42 +656,42 @@ riscv_insn_ext_v_alu_fp = \
 	vmfne_vv \
 
 riscv_insn_ext_v_amo = \
-	vamoswape8_v \
-	vamoadde8_v \
-	vamoande8_v \
-	vamomaxe8_v \
-	vamomaxue8_v \
-	vamomine8_v \
-	vamominue8_v \
-	vamoore8_v \
-	vamoxore8_v \
-	vamoswape16_v \
-	vamoadde16_v \
-	vamoande16_v \
-	vamomaxe16_v \
-	vamomaxue16_v \
-	vamomine16_v \
-	vamominue16_v \
-	vamoore16_v \
-	vamoxore16_v \
-	vamoswape32_v \
-	vamoadde32_v \
-	vamoande32_v \
-	vamomaxe32_v \
-	vamomaxue32_v \
-	vamomine32_v \
-	vamominue32_v \
-	vamoore32_v \
-	vamoxore32_v \
-	vamoswape64_v \
-	vamoadde64_v \
-	vamoande64_v \
-	vamomaxe64_v \
-	vamomaxue64_v \
-	vamomine64_v \
-	vamominue64_v \
-	vamoore64_v \
-	vamoxore64_v \
+	vamoswapei8_v \
+	vamoaddei8_v \
+	vamoandei8_v \
+	vamomaxei8_v \
+	vamomaxuei8_v \
+	vamominei8_v \
+	vamominuei8_v \
+	vamoorei8_v \
+	vamoxorei8_v \
+	vamoswapei16_v \
+	vamoaddei16_v \
+	vamoandei16_v \
+	vamomaxei16_v \
+	vamomaxuei16_v \
+	vamominei16_v \
+	vamominuei16_v \
+	vamoorei16_v \
+	vamoxorei16_v \
+	vamoswapei32_v \
+	vamoaddei32_v \
+	vamoandei32_v \
+	vamomaxei32_v \
+	vamomaxuei32_v \
+	vamominei32_v \
+	vamominuei32_v \
+	vamoorei32_v \
+	vamoxorei32_v \
+	vamoswapei64_v \
+	vamoaddei64_v \
+	vamoandei64_v \
+	vamomaxei64_v \
+	vamomaxuei64_v \
+	vamominei64_v \
+	vamominuei64_v \
+	vamoorei64_v \
+	vamoxorei64_v \
 
 riscv_insn_ext_v_ldst = \
 	vle8_v \
@@ -709,6 +710,22 @@ riscv_insn_ext_v_ldst = \
 	vle16ff_v \
 	vle32ff_v \
 	vle64ff_v \
+	vl1re8_v \
+	vl2re8_v \
+	vl4re8_v \
+	vl8re8_v \
+	vl1re16_v \
+	vl2re16_v \
+	vl4re16_v \
+	vl8re16_v \
+	vl1re32_v \
+	vl2re32_v \
+	vl4re32_v \
+	vl8re32_v \
+	vl1re64_v \
+	vl2re64_v \
+	vl4re64_v \
+	vl8re64_v \
 	vse8_v \
 	vse16_v \
 	vse32_v \
@@ -725,8 +742,10 @@ riscv_insn_ext_v_ldst = \
 	vsuxei16_v \
 	vsuxei32_v \
 	vsuxei64_v \
-	vl1r_v \
 	vs1r_v \
+	vs2r_v \
+	vs4r_v \
+	vs8r_v \
 
 riscv_insn_ext_v_ctrl = \
 	vsetvli \
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index d551062..af913d8 100644
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -794,10 +794,33 @@ disassembler_t::disassembler_t(int xlen)
           ));
       }
     }
+
+    const custom_fmt_t template_insn2[] = {
+      {match_vl1re8_v,   mask_vl1re8_v,   "vl%dre%d.v",   v_ld_unit},
+    };
+
+    for (reg_t i = 0, nf = 7; nf < 4; i++, nf >>= 1) {
+      for (auto item : template_insn) {
+        const reg_t match_nf = nf << 29;
+        char buf[128];
+        sprintf(buf, item.fmt, nf + 1, 8 << elt);
+        add_insn(new disasm_insn_t(
+          buf, item.match | match_nf, item.mask | mask_nf, item.arg
+        ));
+      }
+    }
   }
 
-  DISASM_INSN("vl1r.v", vl1r_v, 0, {&vd, &v_address});
-  DISASM_INSN("vs1r.v", vs1r_v, 0, {&vs3, &v_address});
+  #define DISASM_ST_WHOLE_INSN(name, nf) \
+    add_insn(new disasm_insn_t(#name, match_vs1r_v | (nf << 29), \
+                                      mask_vs1r_v | mask_nf, \
+                                      {&vs3, &v_address}));
+  DISASM_ST_WHOLE_INSN(vs1r.v, 0);
+  DISASM_ST_WHOLE_INSN(vs2r.v, 1);
+  DISASM_ST_WHOLE_INSN(vs4r.v, 3);
+  DISASM_ST_WHOLE_INSN(vs8r.v, 7);
+
+  #undef DISASM_ST_WHOLE_INSN
 
   #define DISASM_OPIV_VXI_INSN(name, sign, suf) \
     add_insn(new disasm_insn_t(#name "." #suf "v", \
@@ -869,19 +892,20 @@ disassembler_t::disassembler_t(int xlen)
 
   //OPFVV/OPFVF
   //0b00_0000
-  DISASM_OPIV_VXI_INSN(vadd,      1, v);
-  DISASM_OPIV_VX__INSN(vsub,      1);
-  DISASM_OPIV__XI_INSN(vrsub,     1);
-  DISASM_OPIV_VX__INSN(vminu,     0);
-  DISASM_OPIV_VX__INSN(vmin,      1);
-  DISASM_OPIV_VX__INSN(vmaxu,     1);
-  DISASM_OPIV_VX__INSN(vmax,      0);
-  DISASM_OPIV_VXI_INSN(vand,      1, v);
-  DISASM_OPIV_VXI_INSN(vor,       1, v);
-  DISASM_OPIV_VXI_INSN(vxor,      1, v);
-  DISASM_OPIV_VXI_INSN(vrgather,  0, v);
-  DISASM_OPIV__XI_INSN(vslideup,  0);
-  DISASM_OPIV__XI_INSN(vslidedown,0);
+  DISASM_OPIV_VXI_INSN(vadd,         1, v);
+  DISASM_OPIV_VX__INSN(vsub,         1);
+  DISASM_OPIV__XI_INSN(vrsub,        1);
+  DISASM_OPIV_VX__INSN(vminu,        0);
+  DISASM_OPIV_VX__INSN(vmin,         1);
+  DISASM_OPIV_VX__INSN(vmaxu,        1);
+  DISASM_OPIV_VX__INSN(vmax,         0);
+  DISASM_OPIV_VXI_INSN(vand,         1, v);
+  DISASM_OPIV_VXI_INSN(vor,          1, v);
+  DISASM_OPIV_VXI_INSN(vxor,         1, v);
+  DISASM_OPIV_VXI_INSN(vrgather,     0, v);
+  DISASM_OPIV_V___INSN(vrgatherei16, 0);
+  DISASM_OPIV__XI_INSN(vslideup,     0);
+  DISASM_OPIV__XI_INSN(vslidedown,   0);
 
   //0b01_0000
   DISASM_OPIV_VXIM_INSN(vadc,    1);
@@ -1155,16 +1179,17 @@ disassembler_t::disassembler_t(int xlen)
   std::vector<const arg_t *> v_fmt_amo = {&x0, &v_address, &vs2, &vd, &opt, &vm};
   for (size_t elt = 0; elt <= 3; ++elt) {
     const custom_fmt_t template_insn[] = {
-      {match_vamoswape8_v | mask_wd,   mask_vamoswape8_v | mask_wd,
-         "%se%d.v", v_fmt_amo_wd},
-      {match_vamoswape8_v,   mask_vamoswape8_v | mask_wd,
-         "%se%d.v", v_fmt_amo},
+      {match_vamoswapei8_v | mask_wd,   mask_vamoswapei8_v | mask_wd,
+         "%sei%d.v", v_fmt_amo_wd},
+      {match_vamoswapei8_v,   mask_vamoswapei8_v | mask_wd,
+         "%sei%d.v", v_fmt_amo},
     };
     std::pair<const char*, reg_t> amo_map[] = {
         {"vamoswap", 0x01ul << 27},
         {"vamoadd",  0x00ul << 27},
         {"vamoxor",  0x04ul << 27},
-        {"vamoor",   0x0cul << 27},
+        {"vamand",   0x0cul << 27},
+        {"vamoor",   0x08ul << 27},
         {"vamomin",  0x10ul << 27},
         {"vamomax",  0x14ul << 27},
         {"vamominu", 0x18ul << 27},