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| author | Andrew Waterman <andrew@sifive.com> | 2020-07-28 20:55:05 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-28 20:55:05 -0700 |
| commit | 6275cdf04d3bbda82e325c4d1959c03e9dedc1bd (patch) | |
| tree | 26b296b742b5ceaa785176e99a836baef29d2dd4 | |
| parent | 67b7edd0270d5d074136eb45474477d15aeee725 (diff) | |
| parent | 308b6db54946d853b47cb5085a06e90aae14145c (diff) | |
| download | spike-6275cdf04d3bbda82e325c4d1959c03e9dedc1bd.zip spike-6275cdf04d3bbda82e325c4d1959c03e9dedc1bd.tar.gz spike-6275cdf04d3bbda82e325c4d1959c03e9dedc1bd.tar.bz2 | |
Merge pull request #517 from riscv/rvv-1.0-vtype
Incorporate RVV 1.0 vtype layout change
| -rw-r--r-- | riscv/decode.h | 4 | ||||
| -rw-r--r-- | riscv/processor.cc | 5 |
2 files changed, 4 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 76d7d90..e7642e6 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -118,8 +118,8 @@ public: uint64_t v_zimm5() { return x(15, 5); } uint64_t v_zimm11() { return x(20, 11); } uint64_t v_lmul() { return x(20, 2); } - uint64_t v_sew() { return 1 << (x(22, 3) + 3); } - uint64_t v_frac_lmul() { return x(25, 1); } + uint64_t v_sew() { return 1 << (x(23, 3) + 3); } + uint64_t v_frac_lmul() { return x(23, 1); } uint64_t v_width() { return x(12, 3); } uint64_t v_mop() { return x(26, 2); } uint64_t v_lumop() { return x(20, 5); } diff --git a/riscv/processor.cc b/riscv/processor.cc index 921487d..798c1c2 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -396,9 +396,8 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT int new_vlmul = 0; if (vtype != newType){ vtype = newType; - vsew = 1 << (BITS(newType, 4, 2) + 3); - new_vlmul = (BITS(newType, 5, 5) << 2) | BITS(newType, 1, 0); - new_vlmul = (int8_t)(new_vlmul << 5) >> 5; + vsew = 1 << (BITS(newType, 5, 3) + 3); + new_vlmul = int8_t(BITS(newType, 2, 0) << 5) >> 5; vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul); vlmax = (VLEN/vsew) * vflmul; vemul = vflmul; |