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authorAnup Patel <anup.patel@wdc.com>2020-06-19 17:56:05 +0530
committerAnup Patel <anup@brainfault.org>2020-07-09 23:04:18 +0530
commit564ed97f618321b8499a3e8837c36f622ee8a893 (patch)
tree81754eab18ac55c64f7c2b3017c451d99bb9d457
parentb75aff9e5d132a16d9326bc0b3bbc724ae3c753c (diff)
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Implement new instructions of hypervisor extension
We add new HFENCE, HLV, and HSV instructions for HS-mode which are defined as part of the RISC-V hypervisor extension. Signed-off-by: Anup Patel <anup.patel@wdc.com>
-rw-r--r--riscv/insns/hfence_gvma.h4
-rw-r--r--riscv/insns/hfence_vvma.h4
-rw-r--r--riscv/insns/hlv_b.h4
-rw-r--r--riscv/insns/hlv_bu.h4
-rw-r--r--riscv/insns/hlv_d.h5
-rw-r--r--riscv/insns/hlv_h.h4
-rw-r--r--riscv/insns/hlv_hu.h4
-rw-r--r--riscv/insns/hlv_w.h4
-rw-r--r--riscv/insns/hlv_wu.h5
-rw-r--r--riscv/insns/hlvx_hu.h4
-rw-r--r--riscv/insns/hlvx_wu.h4
-rw-r--r--riscv/insns/hsv_b.h4
-rw-r--r--riscv/insns/hsv_d.h5
-rw-r--r--riscv/insns/hsv_h.h4
-rw-r--r--riscv/insns/hsv_w.h4
-rw-r--r--riscv/riscv.mk.in18
16 files changed, 81 insertions, 0 deletions
diff --git a/riscv/insns/hfence_gvma.h b/riscv/insns/hfence_gvma.h
new file mode 100644
index 0000000..6ed039a
--- /dev/null
+++ b/riscv/insns/hfence_gvma.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(PRV_S);
+require_novirt();
+MMU.flush_tlb();
diff --git a/riscv/insns/hfence_vvma.h b/riscv/insns/hfence_vvma.h
new file mode 100644
index 0000000..6ed039a
--- /dev/null
+++ b/riscv/insns/hfence_vvma.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(PRV_S);
+require_novirt();
+MMU.flush_tlb();
diff --git a/riscv/insns/hlv_b.h b/riscv/insns/hlv_b.h
new file mode 100644
index 0000000..0fd63e4
--- /dev/null
+++ b/riscv/insns/hlv_b.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int8(RS1));
diff --git a/riscv/insns/hlv_bu.h b/riscv/insns/hlv_bu.h
new file mode 100644
index 0000000..ae00b97
--- /dev/null
+++ b/riscv/insns/hlv_bu.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_uint8(RS1));
diff --git a/riscv/insns/hlv_d.h b/riscv/insns/hlv_d.h
new file mode 100644
index 0000000..cfad660
--- /dev/null
+++ b/riscv/insns/hlv_d.h
@@ -0,0 +1,5 @@
+require_extension('H');
+require_rv64;
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int64(RS1));
diff --git a/riscv/insns/hlv_h.h b/riscv/insns/hlv_h.h
new file mode 100644
index 0000000..bdfc6a7
--- /dev/null
+++ b/riscv/insns/hlv_h.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int16(RS1));
diff --git a/riscv/insns/hlv_hu.h b/riscv/insns/hlv_hu.h
new file mode 100644
index 0000000..8f52eb3
--- /dev/null
+++ b/riscv/insns/hlv_hu.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_uint16(RS1));
diff --git a/riscv/insns/hlv_w.h b/riscv/insns/hlv_w.h
new file mode 100644
index 0000000..33bff44
--- /dev/null
+++ b/riscv/insns/hlv_w.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int32(RS1));
diff --git a/riscv/insns/hlv_wu.h b/riscv/insns/hlv_wu.h
new file mode 100644
index 0000000..94a4553
--- /dev/null
+++ b/riscv/insns/hlv_wu.h
@@ -0,0 +1,5 @@
+require_extension('H');
+require_rv64;
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_uint32(RS1));
diff --git a/riscv/insns/hlvx_hu.h b/riscv/insns/hlvx_hu.h
new file mode 100644
index 0000000..2050291
--- /dev/null
+++ b/riscv/insns/hlvx_hu.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_x_uint16(RS1));
diff --git a/riscv/insns/hlvx_wu.h b/riscv/insns/hlvx_wu.h
new file mode 100644
index 0000000..515b46e
--- /dev/null
+++ b/riscv/insns/hlvx_wu.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_x_uint32(RS1));
diff --git a/riscv/insns/hsv_b.h b/riscv/insns/hsv_b.h
new file mode 100644
index 0000000..e0f1162
--- /dev/null
+++ b/riscv/insns/hsv_b.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint8(RS1, RS2);
diff --git a/riscv/insns/hsv_d.h b/riscv/insns/hsv_d.h
new file mode 100644
index 0000000..6d41fb8
--- /dev/null
+++ b/riscv/insns/hsv_d.h
@@ -0,0 +1,5 @@
+require_extension('H');
+require_rv64;
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint64(RS1, RS2);
diff --git a/riscv/insns/hsv_h.h b/riscv/insns/hsv_h.h
new file mode 100644
index 0000000..f4da613
--- /dev/null
+++ b/riscv/insns/hsv_h.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint16(RS1, RS2);
diff --git a/riscv/insns/hsv_w.h b/riscv/insns/hsv_w.h
new file mode 100644
index 0000000..efa7d97
--- /dev/null
+++ b/riscv/insns/hsv_w.h
@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint32(RS1, RS2);
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 1aa3352..73c4cef 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -739,6 +739,23 @@ riscv_insn_ext_v = \
$(riscv_insn_ext_v_ctrl) \
$(riscv_insn_ext_v_ldst) \
+riscv_insn_ext_h = \
+ hfence_gvma \
+ hfence_vvma \
+ hlv_b \
+ hlv_bu \
+ hlv_h \
+ hlv_hu \
+ hlvx_hu \
+ hlv_w \
+ hlv_wu \
+ hlvx_wu \
+ hlv_d \
+ hsv_b \
+ hsv_h \
+ hsv_w \
+ hsv_d \
+
riscv_insn_priv = \
csrrc \
csrrci \
@@ -765,6 +782,7 @@ riscv_insn_list = \
$(riscv_insn_ext_zfh) \
$(riscv_insn_ext_q) \
$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \
+ $(riscv_insn_ext_h) \
$(riscv_insn_priv) \
riscv_gen_srcs = \