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author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-20 14:53:33 -0700 |
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committer | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-21 10:29:20 -0700 |
commit | c790f73ae94d358e9493187fdbcc9053ed7af7d8 (patch) | |
tree | 307a59c93d234f75234e3cb7d05492a99e3f00b1 | |
parent | 67e205c289becb42b4e8495b46385688c1c167f7 (diff) | |
download | spike-c790f73ae94d358e9493187fdbcc9053ed7af7d8.zip spike-c790f73ae94d358e9493187fdbcc9053ed7af7d8.tar.gz spike-c790f73ae94d358e9493187fdbcc9053ed7af7d8.tar.bz2 |
Vector-fp instructions depend on zve, not F/D
-rw-r--r-- | riscv/isa_parser.h | 2 | ||||
-rw-r--r-- | riscv/v_ext_macros.h | 20 |
2 files changed, 12 insertions, 10 deletions
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index 82c469a..afb49f2 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -104,6 +104,8 @@ public: std::string get_isa_string() const { return isa_string; } reg_t get_vlen() const { return vlen; } reg_t get_elen() const { return elen; } + bool get_zvf() const { return zvf; } + bool get_zvd() const { return zvd; } bool extension_enabled(unsigned char ext) const { return extension_enabled(isa_extension_t(ext)); } diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index a95af3e..3e8a653 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1449,8 +1449,8 @@ reg_t index[P.VU.vlmax]; \ #define VI_VFP_COMMON \ require_fp; \ require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) || \ - (P.VU.vsew == e32 && p->extension_enabled('F')) || \ - (P.VU.vsew == e64 && p->extension_enabled('D'))); \ + (P.VU.vsew == e32 && p->get_isa().get_zvf()) || \ + (P.VU.vsew == e64 && p->get_isa().get_zvd())); \ require_vector(true); \ require(STATE.frm->read() < 0x5); \ reg_t UNUSED vl = P.VU.vl->read(); \ @@ -1662,8 +1662,8 @@ reg_t index[P.VU.vlmax]; \ #define VI_VFP_VV_LOOP_WIDE_REDUCTION(BODY16, BODY32) \ VI_CHECK_REDUCTION(true) \ VI_VFP_COMMON \ - require((P.VU.vsew == e16 && p->extension_enabled('F')) || \ - (P.VU.vsew == e32 && p->extension_enabled('D'))); \ + require((P.VU.vsew == e16 && p->get_isa().get_zvf()) || \ + (P.VU.vsew == e32 && p->get_isa().get_zvd())); \ bool is_active = false; \ switch (P.VU.vsew) { \ case e16: { \ @@ -1948,17 +1948,17 @@ reg_t index[P.VU.vlmax]; \ switch (P.VU.vsew) { \ case e16: \ { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 16, sign), \ - { p->extension_enabled(EXT_ZVFH); }, \ + { require(p->extension_enabled(EXT_ZVFH)); }, \ BODY16); } \ break; \ case e32: \ { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 32, sign), \ - { p->extension_enabled('F'); }, \ + { require(p->get_isa().get_zvf()); }, \ BODY32); } \ break; \ case e64: \ { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 64, sign), \ - { p->extension_enabled('D'); }, \ + { require(p->get_isa().get_zvd()); }, \ BODY64); } \ break; \ default: \ @@ -1972,17 +1972,17 @@ reg_t index[P.VU.vlmax]; \ switch (P.VU.vsew) { \ case e16: \ { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 16, sign), \ - { p->extension_enabled(EXT_ZVFH); }, \ + { require(p->extension_enabled(EXT_ZVFH)); }, \ BODY16); } \ break; \ case e32: \ { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 32, sign), \ - { p->extension_enabled('F'); }, \ + { require(p->get_isa().get_zvf()); }, \ BODY32); } \ break; \ case e64: \ { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 64, sign), \ - { p->extension_enabled('D'); }, \ + { require(p->get_isa().get_zvd()); }, \ BODY64); } \ break; \ default: \ |