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| author | Andrew Waterman <andrew@sifive.com> | 2018-05-04 12:05:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-05-04 12:05:33 -0700 |
| commit | d48f107dba6a96fb827cb47fdf290261feadeb35 (patch) | |
| tree | 8d564cd5560c4dcbc2961c495bd8ac33be8dec1f | |
| parent | d336aee08ba9c5715d5d7836a39003e62ee4ada8 (diff) | |
| download | spike-d48f107dba6a96fb827cb47fdf290261feadeb35.zip spike-d48f107dba6a96fb827cb47fdf290261feadeb35.tar.gz spike-d48f107dba6a96fb827cb47fdf290261feadeb35.tar.bz2 | |
Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"
See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59
| -rw-r--r-- | riscv/insns/c_flwsp.h | 1 | ||||
| -rw-r--r-- | riscv/insns/c_lwsp.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h index d1e14fe..79058c4 100644 --- a/riscv/insns/c_flwsp.h +++ b/riscv/insns/c_flwsp.h @@ -4,5 +4,6 @@ if (xlen == 32) { require_fp; WRITE_FRD(f32(MMU.load_uint32(RVC_SP + insn.rvc_lwsp_imm()))); } else { // c.ldsp + require(insn.rvc_rd() != 0); WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm())); } diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h index ed4dcf3..b3d74db 100644 --- a/riscv/insns/c_lwsp.h +++ b/riscv/insns/c_lwsp.h @@ -1,2 +1,3 @@ require_extension('C'); +require(insn.rvc_rd() != 0); WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm())); |