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| author | Andrew Waterman <andrew@sifive.com> | 2018-05-03 17:14:28 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-05-03 17:14:28 -0700 |
| commit | d336aee08ba9c5715d5d7836a39003e62ee4ada8 (patch) | |
| tree | e9c02e1b420ad64f91a85118495a80352ec1413e | |
| parent | d2e9a109e8f7b851fd153b469cc42a8519d85679 (diff) | |
| download | spike-d336aee08ba9c5715d5d7836a39003e62ee4ada8.zip spike-d336aee08ba9c5715d5d7836a39003e62ee4ada8.tar.gz spike-d336aee08ba9c5715d5d7836a39003e62ee4ada8.tar.bz2 | |
C.LWSP and C.LDSP with rd=0 are legal instructions
This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982
| -rw-r--r-- | riscv/insns/c_flwsp.h | 1 | ||||
| -rw-r--r-- | riscv/insns/c_lwsp.h | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h index 79058c4..d1e14fe 100644 --- a/riscv/insns/c_flwsp.h +++ b/riscv/insns/c_flwsp.h @@ -4,6 +4,5 @@ if (xlen == 32) { require_fp; WRITE_FRD(f32(MMU.load_uint32(RVC_SP + insn.rvc_lwsp_imm()))); } else { // c.ldsp - require(insn.rvc_rd() != 0); WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm())); } diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h index b3d74db..ed4dcf3 100644 --- a/riscv/insns/c_lwsp.h +++ b/riscv/insns/c_lwsp.h @@ -1,3 +1,2 @@ require_extension('C'); -require(insn.rvc_rd() != 0); WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm())); |