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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-20 17:31:11 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-09-25 03:55:11 -0700 |
| commit | 606314955661d65ac080fc9a8ff198cfed8be1ad (patch) | |
| tree | b4bc412f22cd23941cf31cc20944dafc460b5046 | |
| parent | 55ef17645dd61a8e59a826118f23e7077ac9ab26 (diff) | |
| download | spike-606314955661d65ac080fc9a8ff198cfed8be1ad.zip spike-606314955661d65ac080fc9a8ff198cfed8be1ad.tar.gz spike-606314955661d65ac080fc9a8ff198cfed8be1ad.tar.bz2 | |
For backwards compatibility, reset PMP to permit all accesses
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 6221f8b..88e1a63 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -128,6 +128,9 @@ void state_t::reset(reg_t max_isa) tselect = 0; for (unsigned int i = 0; i < num_triggers; i++) mcontrol[i].type = 2; + + pmpcfg[0] = PMP_R | PMP_W | PMP_X | PMP_NAPOT; + pmpaddr[0] = ~reg_t(0); } void processor_t::set_debug(bool value) |