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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-22 14:07:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-22 14:07:45 -0700 |
| commit | 60235e3816220eabc6f6e48d103889300d5547df (patch) | |
| tree | 1d3df46f8a1a967dd3a9429c824affe51c61da5f | |
| parent | b6ec196e9efe33d29d0c9fb80202737719c7730f (diff) | |
| download | spike-60235e3816220eabc6f6e48d103889300d5547df.zip spike-60235e3816220eabc6f6e48d103889300d5547df.tar.gz spike-60235e3816220eabc6f6e48d103889300d5547df.tar.bz2 | |
Make IRQ_COP read-only/undelegable unless coprocessor is present
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 8bcd8e2..4a7d0ec 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -330,7 +330,8 @@ int processor_t::paddr_bits() void processor_t::set_csr(int which, reg_t val) { val = zext_xlen(val); - reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP); + reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP + | ((ext != NULL) << IRQ_COP); reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; switch (which) { |