From 397bb4f347c25142330ab1a74985be041533fe5a Mon Sep 17 00:00:00 2001 From: Thanos Makatos Date: Tue, 22 Jun 2021 14:21:12 +0100 Subject: PCI: handle cache line register (#573) Signed-off-by: Thanos Makatos Reviewed-by: John Levon --- lib/pci.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'lib') diff --git a/lib/pci.c b/lib/pci.c index 1cb0c62..4875b25 100644 --- a/lib/pci.c +++ b/lib/pci.c @@ -233,6 +233,11 @@ pci_hdr_write(vfu_ctx_t *vfu_ctx, const char *buf, loff_t offset) cfg_space->hdr.intr.iline = buf[0]; vfu_log(vfu_ctx, LOG_DEBUG, "ILINE=%0x", cfg_space->hdr.intr.iline); break; + case PCI_CACHE_LINE_SIZE: + cfg_space->hdr.cls = (uint8_t)buf[0]; + vfu_log(vfu_ctx, LOG_DEBUG, "cache line size set to %#hhx", + cfg_space->hdr.cls); + break; case PCI_LATENCY_TIMER: cfg_space->hdr.mlt = (uint8_t)buf[0]; vfu_log(vfu_ctx, LOG_INFO, "set to latency timer to %hhx", -- cgit v1.1