aboutsummaryrefslogtreecommitdiff
path: root/board/freescale/mpc7448hpc2/tsi108_init.c
blob: e1c63f8e375a155f07b100b7229cadcbf75865a1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
/*****************************************************************************
 * (C) Copyright 2003;  Tundra Semiconductor Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *****************************************************************************/

/*----------------------------------------------------------------------------
 * FILENAME: tsi108_init.c
 *
 * Originator: Alex Bounine
 *
 * DESCRIPTION:
 * Initialization code for the Tundra Tsi108 bridge chip
 *---------------------------------------------------------------------------*/

#include <common.h>
#include <74xx_7xx.h>
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <tsi108.h>

DECLARE_GLOBAL_DATA_PTR;

extern void mpicInit (int verbose);

/*
 * Configuration Options
 */

typedef struct {
	ulong upper;
	ulong lower;
} PB2OCN_LUT_ENTRY;

PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
	/* 0 - 7 */
	{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */

	/* 8 - 15 */
	{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */

	/* 16 - 23 */
	{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
	/* 24 - 31 */
	{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
	{0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X  PCI I/O (Byte-Swap + Translate) */
	{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X  PCI Config (Byte-Swap) */

	{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
	{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
	{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
	{0x00000000, 0x00000240}  /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
};

#ifdef CONFIG_SYS_CLK_SPREAD
typedef struct {
	ulong ctrl0;
	ulong ctrl1;
} PLL_CTRL_SET;

/*
 * Clock Generator SPLL0 initialization values
 * PLL0 configuration table for various PB_CLKO freq.
 * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
 * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
 */

static PLL_CTRL_SET pll0_config[8] = {
	{0x00000000, 0x00000000},	/* 0: bypass */
	{0x00000000, 0x00000000},	/* 1: reserved */
	{0x00430044, 0x00000043},	/* 2: CG_PB_CLKO = 183 MHz */
	{0x005c0044, 0x00000039},	/* 3: CG_PB_CLKO = 100 MHz */
	{0x005c0044, 0x00000039},	/* 4: CG_PB_CLKO = 133 MHz */
	{0x004a0044, 0x00000040},	/* 5: CG_PB_CLKO = 167 MHz */
	{0x005c0044, 0x00000039},	/* 6: CG_PB_CLKO = 200 MHz */
	{0x004f0044, 0x0000003e}	/* 7: CG_PB_CLKO = 233 MHz */
};
#endif	/* CONFIG_SYS_CLK_SPREAD */

/*
 * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
 * (based on recommended Tsi108 reference clock 33MHz)
 */
static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };

/*
 * get_board_bus_clk ()
 *
 * returns the bus clock in Hz.
 */
unsigned long get_board_bus_clk (void)
{
	ulong i;

	/* Detect PB clock freq. */
	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */

	return pb_clk_sel[i] * 1000000;
}

/*
 * board_early_init_f ()
 *
 * board-specific initialization executed from flash
 */

int board_early_init_f (void)
{
	ulong i;

	gd->mem_clk = 0;
	i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
			CG_PWRUP_STATUS);
	i = (i >> 20) & 0x07;	/* Get GD PLL multiplier */
	switch (i) {
	case 0:	/* external clock */
		printf ("Using external clock\n");
		break;
	case 1:	/* system clock */
		gd->mem_clk = gd->bus_clk;
		break;
	case 4:	/* 133 MHz */
	case 5:	/* 166 MHz */
	case 6:	/* 200 MHz */
		gd->mem_clk = pb_clk_sel[i] * 1000000;
		break;
	default:
		printf ("Invalid DDR2 clock setting\n");
		return -1;
	}
	printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
	printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
	return 0;
}

/*
 * board_early_init_r() - Tsi108 initialization function executed right after
 * relocation. Contains code that cannot be executed from flash.
 */

int board_early_init_r (void)
{
	ulong temp, i;
	ulong reg_val;
	volatile ulong *reg_ptr;

	reg_ptr =
		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);

	for (i = 0; i < 32; i++) {
		*reg_ptr++ = 0x00000201;	/* SWAP ENABLED */
		*reg_ptr++ = 0x00;
	}

	__asm__ __volatile__ ("eieio");
	__asm__ __volatile__ ("sync");

	/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
		0x80000001);
	__asm__ __volatile__ ("sync");

	/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
	 * read from SDRAM)
	 */

	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
	__asm__ __volatile__ ("sync");

	/*
	 * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
	 * processor bus address space. Immediately after reset LUT and address
	 * translation are disabled for this BAR. Now we have to initialize LUT
	 * and switch from the BOOT mode to the normal operation mode.
	 *
	 * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
	 * and covers 512MB of address space. To allow larger aperture we also
	 * have to relocate register window of Tsi108
	 *
	 * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
	 * mode.
	 *
	 * initialize pointer to LUT associated with PB_OCN_BAR1
	 */
	reg_ptr =
		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);

	for (i = 0; i < 32; i++) {
		*reg_ptr++ = pb2ocn_lut1[i].lower;
		*reg_ptr++ = pb2ocn_lut1[i].upper;
	}

	__asm__ __volatile__ ("sync");

	/* Base addresses for CS0, CS1, CS2, CS3 */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
		0x00000000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
		0x00100000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
		0x00200000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
		0x00300000);
	__asm__ __volatile__ ("sync");

	/* Masks for HLP banks */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
		0xFFF00000);
	__asm__ __volatile__ ("sync");

	/* Set CTRL0 values for banks */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
		0x7FFC44C2);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
		0x7FFC44C0);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
		0x7FFC44C0);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
		0x7FFC44C2);
	__asm__ __volatile__ ("sync");

	/* Set banks to latched mode, enabled, and other default settings */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
		0x7C0F2000);
	__asm__ __volatile__ ("sync");

	/*
	 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
	 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
	 */
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
		0xE0000011);
	__asm__ __volatile__ ("sync");

	/* Make sure that OCN_BAR2 decoder is set (to allow following
	 * immediate read from SDRAM)
	 */

	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
	__asm__ __volatile__ ("sync");

	/*
	 * SRI: At this point we have enabled the HLP banks. That means we can
	 * now read from the NVRAM and initialize the environment variables.
	 * We will over-ride the env_init called in board_init_f
	 * This is really a work-around because, the HLP bank 1
	 * where NVRAM resides is not visible during board_init_f
	 * (arch/powerpc/lib/board.c)
	 * Alternatively, we could use the I2C EEPROM at start-up to configure
	 * and enable all HLP banks and not just HLP 0 as is being done for
	 * Taiga Rev. 2.
	 */

	env_init ();

#ifndef DISABLE_PBM

	/*
	 * For IBM processors we have to set Address-Only commands generated
	 * by PBM that are different from ones set after reset.
	 */

	temp = get_cpu_type ();

	if ((CPU_750FX == temp) || (CPU_750GX == temp))
		out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
			0x00009955);
#endif	/* DISABLE_PBM */

#ifdef CONFIG_PCI
	/*
	 * Initialize PCI/X block
	 */

	/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
		PCI_PFAB_BAR0_UPPER, 0);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
		0xFB000001);
	__asm__ __volatile__ ("sync");

	/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */

	temp =	in32(CONFIG_SYS_TSI108_CSR_BASE +
		TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);

	temp &= ~0xFF00;	/* Clear the BUS_NUM field */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
		temp);

	/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
		0);
	__asm__ __volatile__ ("sync");

	/* This register is on the PCI side to interpret the address it receives
	 * and maps it as a IO address.
	 */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
		0x00000001);
	__asm__ __volatile__ ("sync");

	/*
	 * Map PCI/X Memory Space
	 *
	 * Transactions directed from OCM to PCI Memory Space are directed
	 * from PB to PCI
	 * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
	 * If address remapping is required the corresponding PCI_PFAB_MEM32
	 * and PCI_PFAB_PFMx register groups have to be configured.
	 *
	 * Map the path from the PCI/X bus into the system memory
	 *
	 * The memory mapped window assotiated with PCI P2O_BAR2 provides
	 * access to the system memory without address remapping.
	 * All system memory is opened for accesses initiated by PCI/X bus
	 * masters.
	 *
	 * Initialize LUT associated with PCI P2O_BAR2
	 *
	 * set pointer to LUT associated with PCI P2O_BAR2
	 */

	reg_ptr =
		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);

#ifdef DISABLE_PBM

	/* In case when PBM is disabled (no HW supported cache snoopng on PB)
	 * P2O_BAR2 is directly mapped into the system memory without address
	 * translation.
	 */

	reg_val = 0x00000004;	/* SDRAM port + NO Addr_Translation */

	for (i = 0; i < 32; i++) {
		*reg_ptr++ = reg_val;	/* P2O_BAR2_LUTx */
		*reg_ptr++ = 0;		/* P2O_BAR2_LUT_UPPERx */
	}

	/* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
	reg_val = 0x00007500;
#else

	reg_val = 0x00000002;	/* Destination port = PBM */

	for (i = 0; i < 32; i++) {
		*reg_ptr++ = reg_val;	/* P2O_BAR2_LUTx */
/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
		*reg_ptr++ = 0x40000000;
/* offset = 16MB, address translation is enabled to allow byte swapping */
		reg_val += 0x01000000;
	}

/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
	reg_val = 0x00007100;
#endif

	__asm__ __volatile__ ("eieio");
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
		reg_val);
	__asm__ __volatile__ ("sync");

	/* Set 64-bit PCI bus address for system memory
	 * ( 0 is the best choice for easy mapping)
	 */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
		0x00000000);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
		0x00000000);
	__asm__ __volatile__ ("sync");

#ifndef DISABLE_PBM
	/*
	 *  The memory mapped window assotiated with PCI P2O_BAR3 provides
	 *  access to the system memory using SDRAM OCN port and address
	 *  translation. This is alternative way to access SDRAM from PCI
	 *  required for Tsi108 emulation testing.
	 *  All system memory is opened for accesses initiated by
	 *  PCI/X bus masters.
	 *
	 *  Initialize LUT associated with PCI P2O_BAR3
	 *
	 *  set pointer to LUT associated with PCI P2O_BAR3
	 */
	reg_ptr =
		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);

	reg_val = 0x00000004;	/* Destination port = SDC */

	for (i = 0; i < 32; i++) {
		*reg_ptr++ = reg_val;	/* P2O_BAR3_LUTx */

/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
		*reg_ptr++ = 0;

/* offset = 16MB, address translation is enabled to allow byte swapping */
		reg_val += 0x01000000;
	}

	__asm__ __volatile__ ("eieio");
	__asm__ __volatile__ ("sync");

	/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */

	reg_val =
		in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
		 PCI_P2O_PAGE_SIZES);
	reg_val &= ~0x00FF;
	reg_val |= 0x0071;
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
		reg_val);
	__asm__ __volatile__ ("sync");

	/* Set 64-bit base PCI bus address for window (0x20000000) */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
		0x00000000);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
		0x20000000);
	__asm__ __volatile__ ("sync");

#endif	/* !DISABLE_PBM */

#ifdef ENABLE_PCI_CSR_BAR
	/* open if required access to Tsi108 CSRs from the PCI/X bus */
	/* enable BAR0 on the PCI/X bus */
	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
		TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
	reg_val |= 0x02;
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
		reg_val);
	__asm__ __volatile__ ("sync");

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
		0x00000000);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
		CONFIG_SYS_TSI108_CSR_BASE);
	__asm__ __volatile__ ("sync");

#endif

	/*
	 * Finally enable PCI/X Bus Master and Memory Space access
	 */

	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
	reg_val |= 0x06;
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
	__asm__ __volatile__ ("sync");

#endif	/* CONFIG_PCI */

	/*
	 * Initialize MPIC outputs (interrupt pins):
	 * Interrupt routing on the Grendel Emul. Board:
	 * PB_INT[0] -> INT (CPU0)
	 * PB_INT[1] -> INT (CPU1)
	 * PB_INT[2] -> MCP (CPU0)
	 * PB_INT[3] -> MCP (CPU1)
	 * Set interrupt controller outputs as Level_Sensitive/Active_Low
	 */
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
	__asm__ __volatile__ ("sync");

	/*
	 * Ensure that Machine Check exception is enabled
	 * We need it to support PCI Bus probing (configuration reads)
	 */

	reg_val = mfmsr ();
	mtmsr(reg_val | MSR_ME);

	return 0;
}

/*
 * Needed to print out L2 cache info
 * used in the misc_init_r function
 */

unsigned long get_l2cr (void)
{
	unsigned long l2controlreg;
	asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
	return l2controlreg;
}

/*
 * misc_init_r()
 *
 * various things to do after relocation
 *
 */

int misc_init_r (void)
{
#ifdef CONFIG_SYS_CLK_SPREAD	/* Initialize Spread-Spectrum Clock generation */
	ulong i;

	/* Ensure that Spread-Spectrum is disabled */
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);

	/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
	 * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
	 */

	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
		0x002e0044);	/* D = 0.25% */
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
		0x00000039);	/* BWADJ */

	/* Initialize PLL0: CG_PB_CLKO  */
	/* Detect PB clock freq. */
	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */

	out32 (CONFIG_SYS_TSI108_CSR_BASE +
		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
	out32 (CONFIG_SYS_TSI108_CSR_BASE +
		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);

	/* Wait and set SSEN for both PLL0 and 1 */
	udelay (1000);
	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
		0x802e0044);	/* D=0.25% */
	out32 (CONFIG_SYS_TSI108_CSR_BASE +
		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
		0x80000000 | pll0_config[i].ctrl0);
#endif	/* CONFIG_SYS_CLK_SPREAD */

#ifdef CONFIG_SYS_L2
	l2cache_enable ();
#endif
	printf ("BUS:   %lu MHz\n", gd->bus_clk / 1000000);
	printf ("MEM:   %lu MHz\n", gd->mem_clk / 1000000);

	/*
	 * All the information needed to print the cache details is avaiblable
	 * at this point i.e. above call to l2cache_enable is the very last
	 * thing done with regards to enabling diabling the cache.
	 * So this seems like a good place to print all this information
	 */

	printf ("CACHE: ");
	switch (get_cpu_type()) {
	case CPU_7447A:
		printf ("L1 Instruction cache - 32KB 8-way");
		(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
			printf (" DISABLED\n");
		printf ("L1 Data cache - 32KB 8-way");
		(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
			printf (" DISABLED\n");
		printf ("Unified L2 cache - 512KB 8-way");
		(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
			printf (" DISABLED\n");
		printf ("\n");
		break;

	case CPU_7448:
		printf ("L1 Instruction cache - 32KB 8-way");
		(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
			printf (" DISABLED\n");
		printf ("L1 Data cache - 32KB 8-way");
		(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
			printf (" DISABLED\n");
		printf ("Unified L2 cache - 1MB 8-way");
		(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
			printf (" DISABLED\n");
		break;
	default:
		break;
	}
	return 0;
}