blob: 4cc3defc8828831c16a978a2bdf8a060686aea8f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#include <log.h>
#include <ram.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
#ifndef CONFIG_SUPPORT_SPL
int rv;
struct udevice *dev;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv) {
debug("DRAM init failed: %d\n", rv);
return rv;
}
#endif
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
debug("SPL: booting kernel\n");
/* break into full u-boot on 'c' */
return serial_tstc() && serial_getc() == 'c';
}
#endif
int spl_dram_init(void)
{
struct udevice *dev;
int rv;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv)
debug("DRAM init failed: %d\n", rv);
return rv;
}
void spl_board_init(void)
{
preloader_console_init();
spl_dram_init();
arch_cpu_init(); /* to configure mpu for sdram rw permissions */
}
u32 spl_boot_device(void)
{
/* There is no way to find the boot device so look if there is a valid IVT in RAM for MMC */
u32 nor_ivt = *(u32 *)(CONFIG_SYS_LOAD_ADDR - 0xC00);
if (nor_ivt == 0x402000d1)
return BOOT_DEVICE_MMC1;
return BOOT_DEVICE_NOR;
}
#endif
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
|