blob: e6b6130de253c3f46811329c507997518d6daf0f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
|
menu "LCRR - Clock Ratio Register register"
if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
choice
prompt "DLL bypass"
config LCRR_DBYP_UNSET
bool "Don't set value"
config LCRR_DBYP_PLL_ENABLED
bool "PLL enabled"
config LCRR_DBYP_PLL_BYPASSED
bool "PLL bypassed"
endchoice
endif
if ARCH_MPC834X || ARCH_MPC8360
choice
prompt "Additional delay cycles for SDRAM control signals"
config LCRR_BUFCMDC_UNSET
bool "Don't set value"
config LCRR_BUFCMDC_4
bool "4"
config LCRR_BUFCMDC_1
bool "1"
config LCRR_BUFCMDC_2
bool "2"
config LCRR_BUFCMDC_3
bool "3"
endchoice
choice
prompt "Extended CAS latency"
config LCRR_ECL_UNSET
bool "Don't set value"
config LCRR_ECL_4
bool "4"
config LCRR_ECL_5
bool "5"
config LCRR_ECL_6
bool "6"
config LCRR_ECL_7
bool "7"
endchoice
endif # ARCH_MPC834X || ARCH_MPC8360
if !ARCH_MPC8308
choice
prompt "External address delay cycles"
config LCRR_EADC_UNSET
bool "Don't set value"
config LCRR_EADC_4
bool "4"
config LCRR_EADC_1
bool "1"
config LCRR_EADC_2
bool "2"
config LCRR_EADC_3
bool "3"
endchoice
endif # !ARCH_MPC8308
choice
prompt "System clock divider"
config LCRR_CLKDIV_UNSET
bool "Don't set value"
config LCRR_CLKDIV_2
bool "2"
config LCRR_CLKDIV_4
bool "4"
config LCRR_CLKDIV_8
bool "8"
endchoice
config LCRR_DBYP
hex
default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
config LCRR_BUFCMDC
hex
default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
default 0x10000000 if LCRR_BUFCMDC_1
default 0x20000000 if LCRR_BUFCMDC_2
default 0x30000000 if LCRR_BUFCMDC_3
config LCRR_ECL
hex
default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
default 0x1000000 if LCRR_ECL_5
default 0x2000000 if LCRR_ECL_6
default 0x3000000 if LCRR_ECL_7
config LCRR_EADC
hex
default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
default 0x10000 if LCRR_EADC_1
default 0x20000 if LCRR_EADC_2
default 0x30000 if LCRR_EADC_3
config LCRR_CLKDIV
hex
default 0x0 if LCRR_CLKDIV_UNSET
default 0x2 if LCRR_CLKDIV_2
default 0x4 if LCRR_CLKDIV_4
default 0x8 if LCRR_CLKDIV_8
endmenu
|
