aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/mach-mtmips/mt7628/serial.c
blob: a7d324792d739ac8e18e217acf67762ae3cff903 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 MediaTek Inc.
 *
 * Author:  Weijie Gao <weijie.gao@mediatek.com>
 */

#include <common.h>
#include <asm/io.h>
#include "mt7628.h"

void mtmips_spl_serial_init(void)
{
#ifdef CONFIG_SPL_SERIAL_SUPPORT
	void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);

#if CONFIG_CONS_INDEX == 1
	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
#elif CONFIG_CONS_INDEX == 2
	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
#elif CONFIG_CONS_INDEX == 3
	setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
#ifdef CONFIG_SPL_UART2_SPIS_PINMUX
	setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
		      1 << UART2_MODE_S);
#else
	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
		      1 << SPIS_MODE_S);
#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
#endif /* CONFIG_CONS_INDEX */
#endif /* CONFIG_SPL_SERIAL_SUPPORT */
}