blob: 6c9332e2bd9746f4dc3ad7cf626237795835f136 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* K3: AM64 SoC definitions, structures etc.
*
* (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_AM64_HARDWARE_H
#define __ASM_ARCH_AM64_HARDWARE_H
#define PADCFG_MMR1_BASE 0x000f0000
#define MCU_PADCFG_MMR1_BASE 0x04080000
#define WKUP_CTRL_MMR0_BASE 0x43000000
#define MCU_CTRL_MMR0_BASE 0x04500000
#define CTRL_MMR0_BASE 0x43000000
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
/* After the cfg mask and shifts have been applied */
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
/* Use Last 2K as Scratch pad */
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800
#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
|
