blob: dfdb6c7e1b9e36c082a326f1eff34adcd71908ac (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
/*
* clocks_am33xx.h
*
* AM33xx clock define
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
/* MAIN PLL Fdll supported frequencies */
#define MPUPLL_M_1000 1000
#define MPUPLL_M_800 800
#define MPUPLL_M_720 720
#define MPUPLL_M_600 600
#define MPUPLL_M_500 500
#define MPUPLL_M_300 300
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#define CM_DLL_CTRL_NO_OVERRIDE 0x0
#define CM_DLL_READYST 0x4
extern void enable_dmm_clocks(void);
extern const struct dpll_params dpll_core_opp100;
extern struct dpll_params dpll_mpu_opp100;
#endif /* endif _CLOCKS_AM33XX_H_ */
|
