1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
#include "rockchip-u-boot.dtsi"
#include <dt-bindings/phy/phy.h>
/ {
dmc {
compatible = "rockchip,rk3588-dmc";
bootph-all;
status = "okay";
};
usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
usb_host0_ohci: usb@fc840000 {
compatible = "generic-ohci";
reg = <0x0 0xfc840000 0x0 0x40000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
usb_host1_ehci: usb@fc880000 {
compatible = "generic-ehci";
reg = <0x0 0xfc880000 0x0 0x40000>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
usb_host1_ohci: usb@fc8c0000 {
compatible = "generic-ohci";
reg = <0x0 0xfc8c0000 0x0 0x40000>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
pmu1_grf: syscon@fd58a000 {
bootph-all;
compatible = "rockchip,rk3588-pmu1-grf", "syscon";
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfd5bc000 0x0 0x100>;
};
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5d8000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy2: usb2-phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
status = "disabled";
u2phy2_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5dc000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy3: usb2-phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
status = "disabled";
u2phy3_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x40 0x4f>;
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
<0 0 0 2 &pcie2x1l2_intc 1>,
<0 0 0 3 &pcie2x1l2_intc 2>,
<0 0 0 4 &pcie2x1l2_intc 3>;
linux,pci-domain = <4>;
num-ib-windows = <8>;
num-ob-windows = <8>;
num-viewport = <4>;
max-link-speed = <2>;
msi-map = <0x4000 &gic 0x4000 0x1000>;
num-lanes = <1>;
phys = <&combphy0_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
reg = <0xa 0x41000000 0x0 0x00400000>,
<0x0 0xfe190000 0x0 0x00010000>,
<0x0 0xf4000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
reset-names = "pcie", "periph";
rockchip,pipe-grf = <&php_grf>;
status = "disabled";
pcie2x1l2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
};
};
sfc: spi@fe2b0000 {
compatible = "rockchip,sfc";
reg = <0x0 0xfe2b0000 0x0 0x4000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
status = "disabled";
};
otp: nvmem@fecc0000 {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc0000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
cpu_id: id@7 {
reg = <0x07 0x10>;
};
};
rng: rng@fe378000 {
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
status = "disabled";
};
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
<&cru PCLK_PHP_ROOT>;
clock-names = "refclk", "apbclk", "phpclk";
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
status = "disabled";
};
};
&xin24m {
bootph-all;
status = "okay";
};
&cru {
bootph-pre-ram;
status = "okay";
};
&sys_grf {
bootph-pre-ram;
status = "okay";
};
&scmi {
bootph-pre-ram;
};
&scmi_clk {
bootph-pre-ram;
};
&sdmmc {
bootph-pre-ram;
u-boot,spl-fifo-mode;
};
&sdhci {
bootph-pre-ram;
u-boot,spl-fifo-mode;
};
&uart2 {
clock-frequency = <24000000>;
bootph-pre-ram;
status = "okay";
};
&ioc {
bootph-pre-ram;
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
&binman {
simple-bin-spi {
mkimage {
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
offset = <0x8000>;
};
};
};
#endif
|