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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include "rockchip-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
};
chosen {
u-boot,spl-boot-order = &sdhci, &sdmmc0;
};
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
bootph-all;
status = "okay";
};
otp: nvmem@fe38c000 {
compatible = "rockchip,rk3568-otp";
reg = <0x0 0xfe38c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
cpu_id: id@a {
reg = <0x0a 0x10>;
};
};
};
&combphy1 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&cru {
bootph-all;
status = "okay";
};
&pmucru {
bootph-all;
status = "okay";
};
&grf {
bootph-all;
status = "okay";
};
&pmugrf {
bootph-all;
status = "okay";
};
&sdhci {
bootph-pre-ram;
status = "okay";
};
&sdmmc0 {
bootph-pre-ram;
status = "okay";
};
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