From 6a1c7cef14a41ade84bccdded1fd87b908b6958c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 6 Jul 2015 12:54:24 -0600 Subject: dm: test: Add tests for the clk uclass Add tests of each API call using a sandbox clock device. Signed-off-by: Simon Glass --- test/dm/Makefile | 1 + test/dm/clk.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 test/dm/clk.c (limited to 'test') diff --git a/test/dm/Makefile b/test/dm/Makefile index 19ad2fb..7947545 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_UT_DM) += test-uclass.o # subsystem you must add sandbox tests here. obj-$(CONFIG_UT_DM) += core.o ifneq ($(CONFIG_SANDBOX),) +obj-$(CONFIG_CLK) += clk.o obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_DM_GPIO) += gpio.o obj-$(CONFIG_DM_I2C) += i2c.o diff --git a/test/dm/clk.c b/test/dm/clk.c new file mode 100644 index 0000000..9ff6d95 --- /dev/null +++ b/test/dm/clk.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Test that we can find and adjust clocks */ +static int dm_test_clk_base(struct unit_test_state *uts) +{ + struct udevice *clk; + ulong rate; + + ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk)); + rate = clk_get_rate(clk); + ut_asserteq(SANDBOX_CLK_RATE, rate); + ut_asserteq(-EINVAL, clk_set_rate(clk, 0)); + ut_assertok(clk_set_rate(clk, rate * 2)); + ut_asserteq(SANDBOX_CLK_RATE * 2, clk_get_rate(clk)); + + return 0; +} +DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that peripheral clocks work as expected */ +static int dm_test_clk_periph(struct unit_test_state *uts) +{ + struct udevice *clk; + ulong rate; + + ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk)); + rate = clk_set_periph_rate(clk, PERIPH_ID_COUNT, 123); + ut_asserteq(-EINVAL, rate); + ut_asserteq(1, IS_ERR_VALUE(rate)); + + rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 123); + ut_asserteq(0, rate); + ut_asserteq(123, clk_get_periph_rate(clk, PERIPH_ID_SPI)); + + rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234); + ut_asserteq(123, rate); + + rate = clk_set_periph_rate(clk, PERIPH_ID_I2C, 567); + + rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234); + ut_asserteq(1234, rate); + + ut_asserteq(567, clk_get_periph_rate(clk, PERIPH_ID_I2C)); + + return 0; +} +DM_TEST(dm_test_clk_periph, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -- cgit v1.1