From 074596c0b5f4e9a3642a3159a9fc7f8b8064c18a Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 7 Apr 2016 16:22:21 +0800 Subject: armv8/ls1043: Add workaround for DDR erratum A-008850 Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/fsl_ddr_sdram.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index cf316a4..44ae7fb 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + /* DDR_MD_CNTL */ #define MD_CNTL_MD_EN 0x80000000 #define MD_CNTL_CS_SEL_CS0 0x00000000 -- cgit v1.1 From 4a68489e12313a7fa8740463dee0eea2985eb563 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Mar 2016 13:50:22 +0800 Subject: drivers/ddr/fsl: update workaround for erratum A-008511 Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/fsl_ddr_sdram.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 44ae7fb..acddf14 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -189,6 +189,9 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_29 register */ +#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ + #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) -- cgit v1.1 From 5fc62fe57097e195a8047859cd3c278a5d6790b6 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Mar 2016 13:50:23 +0800 Subject: driver/ddr/fsl: Add workaround for erratum A-009801 The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/fsl_ddr_sdram.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index acddf14..486e47e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -189,6 +189,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_26 register */ +#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */ +#define DDR_CAS_TO_PRE_SUB_SHIFT 12 + /* DEBUG_29 register */ #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ -- cgit v1.1 From bcb55f67f22b297d6c10e039bfcef9847a20fbfb Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Wed, 6 Apr 2016 22:25:51 +0530 Subject: armv8: ls2080: enable sec_init in U-Boot Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index a3aad1b..c78aeb5 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -26,6 +26,8 @@ /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* Link Definitions */ #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x80400000 @@ -292,4 +294,10 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #endif /* __LS2_COMMON_H */ -- cgit v1.1 From 7ad9cc969b00cd5e238f4a194f0e974d74706b8e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 19 Apr 2016 08:53:42 +0530 Subject: armv8: ls2080a: update eth prime As per new PHY framework, DPNI naming convetion is no more used. Use new naming convention. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080aqds.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 2d7567f..16a536a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -374,7 +374,7 @@ unsigned long get_board_ddr_clk(void); #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 5bec509..45827f6 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -366,7 +366,7 @@ unsigned long get_board_sys_clk(void); #define AQR405_IRQ_MASK 0x36 #define CONFIG_MII -#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE #define CONFIG_PHY_AQUANTIA #endif -- cgit v1.1 From 1297cdb452fcdc6e7149c6761e43629f9c732010 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Mon, 25 Apr 2016 16:53:53 +0800 Subject: armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabled IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 54968b5..a7d49ed 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -257,8 +257,13 @@ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" +#endif #define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ -- cgit v1.1 From 76394c9c9139b82e21a6e52da0e7341a3374f4be Mon Sep 17 00:00:00 2001 From: Alex Porosanu Date: Fri, 29 Apr 2016 15:18:00 +0300 Subject: crypto/fsl: add support for multiple SEC engines initialization For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu Reviewed-by: York Sun --- include/fsl_sec.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/fsl_sec.h b/include/fsl_sec.h index a52110a..bffabc8 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -294,8 +294,6 @@ struct sg_entry { #endif -int sec_init(void); - /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext @@ -305,6 +303,10 @@ int sec_init(void); */ int blob_dek(const u8 *src, u8 *dst, u8 len); +#if defined(CONFIG_PPC_C29X) +int sec_init_idx(uint8_t); +#endif +int sec_init(void); #endif #endif /* __FSL_SEC_H */ -- cgit v1.1 From 7942550a146f3eaf00add0e13442946365cc9775 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 29 Apr 2016 22:07:21 +0800 Subject: armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 6d35be2..39687cf 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -253,6 +253,7 @@ #define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#define AQR105_IRQ_MASK 0x40000000 #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 -- cgit v1.1 From bc323b3fa7cbf1008f02d342c0505231961b5fa6 Mon Sep 17 00:00:00 2001 From: Po Liu Date: Wed, 18 May 2016 10:09:38 +0800 Subject: armv8: ls1043ardb: enable scsi command and pcie to sata converter Enable scsi command and pcie to sata chip 88SE9170. Signed-off-by: Po Liu Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 39687cf..aca8d95 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -286,6 +286,27 @@ #define CONFIG_USB_STORAGE #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_CMD_SCSI +#ifndef CONFIG_CMD_FAT +#define CONFIG_CMD_FAT +#endif +#ifndef CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT2 +#endif +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 2 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define SCSI_VEND_ID 0x1b4b +#define SCSI_DEV_ID 0x9170 +#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_PCI + #include #endif /* __LS1043ARDB_H__ */ -- cgit v1.1