From 66869f955417b89dbf6b7cbb72738b2205a26bf8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 19 Mar 2015 09:30:26 -0700 Subject: drivers/ddr/fsl: Update DDR driver for DDR4 Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun --- include/fsl_ddr.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'include/fsl_ddr.h') diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index feccef9..4099a74 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -34,9 +34,7 @@ #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) #endif -#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR - -u32 fsl_ddr_get_version(void); +u32 fsl_ddr_get_version(unsigned int ctrl_num); #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* -- cgit v1.1