From 1bf29b3d5571bed2b61581e839599337968deb80 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:18:15 +0200 Subject: mmc: dw_mmc: Fix cache alignment issue The DMA descriptors used by the DW MMC block must be aligned to cacheline size, otherwise we are unable to properly flush/inval cache over them and we get data corruption. The reason I chose this approach of expanding the structure is because the driver allocates the descriptors in bulk. This approach does waste space by inserting slop inbetween the descriptors, but it makes access to the descriptors easy as the compiler does know the real size of the structure. It also makes cache operations easy, since the size of the structure is cache aligned and the structure start address is as well. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Pantelis Antoniou Acked-by: Pavel Machek --- include/dwmmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/dwmmc.h') diff --git a/include/dwmmc.h b/include/dwmmc.h index b67f11b..109f7c8 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -157,7 +157,7 @@ struct dwmci_idmac { u32 cnt; u32 addr; u32 next_addr; -}; +} __aligned(ARCH_DMA_MINALIGN); static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) { -- cgit v1.1