From a4f2d83414557f2ad7b63d537e2c31790d0f184d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 22 Sep 2021 18:29:08 +0200 Subject: mtd: spi: nor: force mtd name to "nor%d" Force the mtd name of spi-nor to "nor" + the driver sequence number: "nor0", "nor1"... beginning after the existing nor devices. This patch is coherent with existing "nand" and "spi-nand" mtd device names. When CFI MTD NOR device are supported, the spi-nor index is chosen after the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS. When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config is replaced by to cfi_flash_num_flash_banks in the include file mtd/cfi_flash.h. This generic name "nor%d" can be use to identify the mtd spi-nor device without knowing the real device name or the DT path of the device, used with API get_mtd_device_nm() and is used in mtdparts command. This patch also avoids issue when the same NOR device is present 2 times, for example on STM32MP15F-EV1: STM32MP> mtd list SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \ total 64 MiB List of MTD devices: * nand0 - type: NAND flash - block size: 0x40000 bytes - min I/O: 0x1000 bytes - OOB size: 224 bytes - OOB available: 118 bytes - ECC strength: 8 bits - ECC step size: 512 bytes - bitflip threshold: 6 bits - 0x000000000000-0x000040000000 : "nand0" * mx66l51235l - device: mx66l51235l@0 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@0 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" * mx66l51235l - device: mx66l51235l@1 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@1 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" The same mtd name "mx66l51235l" identify the 2 instances mx66l51235l@0 and mx66l51235l@1. This patch fixes a ST32CubeProgrammer / stm32prog command issue with nor0 target on STM32MP157C-EV1 board introduced by commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled") Signed-off-by: Patrick Delaunay [trini: Add to for DM_MAX_SEQ_STR] Signed-off-by: Tom Rini --- drivers/mtd/spi/spi-nor-core.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d5d905f..f1b4e5e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -26,6 +27,7 @@ #include #include +#include #include #include @@ -3664,6 +3666,11 @@ int spi_nor_scan(struct spi_nor *nor) struct mtd_info *mtd = &nor->mtd; struct spi_slave *spi = nor->spi; int ret; + int cfi_mtd_nb = 0; + +#ifdef CONFIG_SYS_MAX_FLASH_BANKS + cfi_mtd_nb = CONFIG_SYS_MAX_FLASH_BANKS; +#endif /* Reset SPI protocol for all commands. */ nor->reg_proto = SNOR_PROTO_1_1_1; @@ -3715,8 +3722,12 @@ int spi_nor_scan(struct spi_nor *nor) if (ret) return ret; - if (!mtd->name) - mtd->name = info->name; + if (!mtd->name) { + sprintf(nor->mtd_name, "%s%d", + MTD_DEV_TYPE(MTD_DEV_TYPE_NOR), + cfi_mtd_nb + dev_seq(nor->dev)); + mtd->name = nor->mtd_name; + } mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; @@ -3821,7 +3832,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->rdsr_dummy = params.rdsr_dummy; nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes; - nor->name = mtd->name; + nor->name = info->name; nor->size = mtd->size; nor->erase_size = mtd->erasesize; nor->sector_size = mtd->erasesize; -- cgit v1.1 From b81ce79df091834430dce72f0e4d1451f25fc8f7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 20:28:24 +0200 Subject: mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0 Before e2e95e5e254 ("spi: Update speed/mode on change") most systems silently defaulted to SF bus mode 0. Now the mode is always updated, which causes breakage. It seems most SF which are used as boot media operate in bus mode 0, so switch that as the default. This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked as those might need mode 3. Signed-off-by: Marek Vasut Cc: Aleksandar Gerasimovski Cc: Andreas Biessmann Cc: Eugen Hristev Cc: Michal Simek Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Peng Fan Cc: Siew Chin Lim Cc: Tom Rini Cc: Valentin Longchamp Cc: Vignesh Raghavendra --- drivers/mtd/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index b2291f7..f03fe05 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -57,7 +57,7 @@ config SF_DEFAULT_CS config SF_DEFAULT_MODE hex "SPI Flash default mode (see include/spi.h)" depends on SPI_FLASH || DM_SPI_FLASH - default 3 + default 0 help The default mode may be provided by the platform to handle the common case when only a single serial -- cgit v1.1 From b8919eaa6835c8a606569ea596dd4ed209bd1d67 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 13 Sep 2021 16:25:53 +0200 Subject: mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interface nand_dt_init() is still using fdtdec_xx() interface. If OF_LIVE flag is enabled, dt property can't be get anymore. Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue. For doing this, node parameter type must be ofnode. First idea was to convert "node" parameter to ofnode type inside nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode() is not bijective, in case OF_LIVE flag is enabled, it performs an assert(). So, this leads to update nand_chip struct flash_node field from int to ofnode and to update all nand_dt_init() callers. Signed-off-by: Patrice Chotard --- drivers/mtd/nand/raw/denali.c | 2 +- drivers/mtd/nand/raw/mxs_nand.c | 2 +- drivers/mtd/nand/raw/nand_base.c | 27 +++++++++++---------------- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 2 +- drivers/mtd/nand/raw/sunxi_nand.c | 2 +- 5 files changed, 15 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index ab91db8..c827f80 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -1246,7 +1246,7 @@ int denali_init(struct denali_nand_info *denali) denali->active_bank = DENALI_INVALID_BANK; - chip->flash_node = dev_of_offset(denali->dev); + chip->flash_node = dev_ofnode(denali->dev); /* Fallback to the default name if DT did not give "label" property */ if (!mtd->name) mtd->name = "denali-nand"; diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index e6bbfac..748056a 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1379,7 +1379,7 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) nand->options |= NAND_NO_SUBPAGE_WRITE; if (nand_info->dev) - nand->flash_node = dev_of_offset(nand_info->dev); + nand->flash_node = dev_ofnode(nand_info->dev); nand->cmd_ctrl = mxs_nand_cmd_ctrl; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 3679ee7..b1fd779 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -29,9 +29,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include -#if CONFIG_IS_ENABLED(OF_CONTROL) -#include -#endif #include #include #include @@ -4576,23 +4573,20 @@ ident_done: EXPORT_SYMBOL(nand_get_flash_type); #if CONFIG_IS_ENABLED(OF_CONTROL) -#include -DECLARE_GLOBAL_DATA_PTR; -static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) +static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) { int ret, ecc_mode = -1, ecc_strength, ecc_step; - const void *blob = gd->fdt_blob; const char *str; - ret = fdtdec_get_int(blob, node, "nand-bus-width", -1); + ret = ofnode_read_s32_default(node, "nand-bus-width", -1); if (ret == 16) chip->options |= NAND_BUSWIDTH_16; - if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt")) + if (ofnode_read_bool(node, "nand-on-flash-bbt")) chip->bbt_options |= NAND_BBT_USE_FLASH; - str = fdt_getprop(blob, node, "nand-ecc-mode", NULL); + str = ofnode_read_string(node, "nand-ecc-mode"); if (str) { if (!strcmp(str, "none")) ecc_mode = NAND_ECC_NONE; @@ -4608,9 +4602,10 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) ecc_mode = NAND_ECC_SOFT_BCH; } - - ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1); - ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1); + ecc_strength = ofnode_read_s32_default(node, + "nand-ecc-strength", -1); + ecc_step = ofnode_read_s32_default(node, + "nand-ecc-step-size", -1); if ((ecc_step >= 0 && !(ecc_strength >= 0)) || (!(ecc_step >= 0) && ecc_strength >= 0)) { @@ -4627,13 +4622,13 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) if (ecc_step > 0) chip->ecc.size = ecc_step; - if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL)) + if (ofnode_read_bool(node, "nand-ecc-maximize")) chip->ecc.options |= NAND_ECC_MAXIMIZE; return 0; } #else -static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) +static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) { return 0; } @@ -4657,7 +4652,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, struct nand_flash_dev *type; int ret; - if (chip->flash_node) { + if (ofnode_valid(chip->flash_node)) { ret = nand_dt_init(mtd, chip, chip->flash_node); if (ret) return ret; diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index fd81a95..e17f1f8 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -823,7 +823,7 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) nand->cs_used[i] = cs[i]; } - nand->chip.flash_node = ofnode_to_offset(node); + nand->chip.flash_node = node; return 0; } diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 7bc6ec7..c378f08 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1711,7 +1711,7 @@ static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum) * in the DT. */ nand->ecc.mode = NAND_ECC_HW; - nand->flash_node = node; + nand->flash_node = offset_to_ofnode(node); nand->select_chip = sunxi_nfc_select_chip; nand->cmd_ctrl = sunxi_nfc_cmd_ctrl; nand->read_buf = sunxi_nfc_read_buf; -- cgit v1.1 From 1db1acbb848ef1b10eccedb52edd6c37078bbd38 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 28 Sep 2021 11:30:27 +0530 Subject: clk: versal: Enable only GATE type clocks Clocks should be enabled or disabled only if they are of GATE type clocks. If they are not of GATE type clocks, don't touch them. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/1632808827-6109-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek --- drivers/clk/clk_versal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 62523d2..a9dd57b 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk) clk_id = priv->clk[clk->id].clk_id; - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + if (versal_clock_gate(clk_id)) + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + + return 0; } static struct clk_ops versal_clk_ops = { -- cgit v1.1 From 8c287ed8c3a392d2fd717054511b53851bce02f0 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Tue, 28 Sep 2021 11:31:58 +0530 Subject: watchdog: versal: Add support for basic window watchdog Existing driver uses generic watchdog mode which generates a signal to PLM firmware, but the signal cannot be used to reset the system. Change driver to use window watchdog basic mode. This window watchdog mode generates a signal to PLM firmware which decides what action to take upon expiry of watchdog. Timeout value for xlnx_wwdt_start will come in milli seconds from wdt framework. Make changes to load count value accordingly. Add checks before loading the timer for min and max possible values. Fix authour email id of Ashok Reddy Soma to long email id. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/1632808919-8600-2-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek --- drivers/watchdog/xilinx_wwdt.c | 98 ++++++++++++++++++++++++++---------------- 1 file changed, 60 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index c8e6c60..d8b2ae7 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -3,7 +3,7 @@ * Xilinx window watchdog timer driver. * * Author(s): Michal Simek - * Ashok Reddy Soma + * Ashok Reddy Soma * * Copyright (c) 2020, Xilinx Inc. */ @@ -23,13 +23,22 @@ /* Generic Control/Status Register Masks */ #define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */ -/* Register offsets for the Wdt device */ -#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */ -#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */ -#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */ -#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */ -#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */ -#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */ +/* Register offsets for the WWDT device */ +#define XWT_WWDT_MWR_OFFSET 0x00 +#define XWT_WWDT_ESR_OFFSET 0x04 +#define XWT_WWDT_FCR_OFFSET 0x08 +#define XWT_WWDT_FWR_OFFSET 0x0c +#define XWT_WWDT_SWR_OFFSET 0x10 +#define XWT_WWDT_CNT_MIN 1 +#define XWT_WWDT_CNT_MAX 0xffffffff + +/* Master Write Control Register Masks */ +#define XWT_WWDT_MWR_MASK BIT(0) + +/* Enable and Status Register Masks */ +#define XWT_WWDT_ESR_WINT_MASK BIT(16) +#define XWT_WWDT_ESR_WSW_MASK BIT(8) +#define XWT_WWDT_ESR_WEN_MASK BIT(0) struct xlnx_wwdt_priv { bool enable_once; @@ -43,16 +52,23 @@ struct xlnx_wwdt_plat { static int xlnx_wwdt_reset(struct udevice *dev) { + u32 esr; struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); - regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK); + regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); + regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); + esr |= XWT_WWDT_ESR_WINT_MASK; + esr &= ~XWT_WWDT_ESR_WSW_MASK; + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); + regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); + esr |= XWT_WWDT_ESR_WSW_MASK; + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); return 0; } static int xlnx_wwdt_stop(struct udevice *dev) { - u32 csr; struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); if (wdt->enable_once) { @@ -60,10 +76,9 @@ static int xlnx_wwdt_stop(struct udevice *dev) return -EBUSY; } - /* Disable the generic watchdog timer */ - regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); - csr &= ~(XWT_WWCSR_GWEN_MASK); - regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + /* Disable the window watchdog timer */ + regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK); clk_disable(&wdt->clk); @@ -72,11 +87,11 @@ static int xlnx_wwdt_stop(struct udevice *dev) return 0; } -static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) +static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { int ret; - u32 csr; - u64 count; + u32 esr; + u64 count, timeout; unsigned long clock_f; struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); @@ -88,36 +103,43 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f); + /* Convert timeout from msec to sec */ + timeout = timeout_ms / 1000; + /* Calculate timeout count */ count = timeout * clock_f; + /* Count should be at least 1 */ + if (count < XWT_WWDT_CNT_MIN) { + debug("%s: watchdog won't fire with 0 ticks\n", __func__); + count = XWT_WWDT_CNT_MIN; + } + + /* Limit the count to maximum possible value */ + if (count > XWT_WWDT_CNT_MAX) { + debug("%s: maximum watchdog timeout exceeded\n", __func__); + count = XWT_WWDT_CNT_MAX; + } + ret = clk_enable(&wdt->clk); if (ret) { dev_err(dev, "failed to enable clock\n"); return ret; } - /* - * Timeout count is half as there are two windows - * first window overflow is ignored (interrupt), - * reset is only generated at second window overflow - */ - count = count >> 1; - - /* Disable the generic watchdog timer */ - regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); - csr &= ~(XWT_WWCSR_GWEN_MASK); - regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); - - /* Set compare and offset registers for generic watchdog timeout */ - regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count); - regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0); - regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count); - - /* Enable the generic watchdog timer */ - regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); - csr |= (XWT_WWCSR_GWEN_MASK); - regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + /* Disable the window watchdog timer */ + regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK); + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK); + + /* Set first window and second window registers with timeout */ + regmap_write(wdt->regs, XWT_WWDT_FWR_OFFSET, 0); /* No pre-timeout */ + regmap_write(wdt->regs, XWT_WWDT_SWR_OFFSET, (u32)count); + regmap_write(wdt->regs, XWT_WWDT_FCR_OFFSET, 0); + + /* Enable the window watchdog timer */ + regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr); + esr |= XWT_WWDT_ESR_WEN_MASK; + regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr); return 0; } -- cgit v1.1 From dced079c53b283e15f04282f405de410a9be584d Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Tue, 28 Sep 2021 11:31:59 +0530 Subject: watchdog: versal: Add support for expire now Wdt expire command makes the wdt to count least possible ticks(1) and expires immediately. Add expire_now option to the xlnx_wwdt_ops and implement it by calling xlnx_wwdt_start() with minimum possible count(1). Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/1632808919-8600-3-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek --- drivers/watchdog/xilinx_wwdt.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index d8b2ae7..d582e3c 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -144,6 +144,11 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) return 0; } +static int xlnx_wwdt_expire_now(struct udevice *dev, ulong flags) +{ + return xlnx_wwdt_start(dev, XWT_WWDT_CNT_MIN, flags); +} + static int xlnx_wwdt_probe(struct udevice *dev) { int ret; @@ -182,6 +187,7 @@ static const struct wdt_ops xlnx_wwdt_ops = { .start = xlnx_wwdt_start, .reset = xlnx_wwdt_reset, .stop = xlnx_wwdt_stop, + .expire_now = xlnx_wwdt_expire_now, }; static const struct udevice_id xlnx_wwdt_ids[] = { -- cgit v1.1