From 9fd406de522ef1fb5863837eee1dd9bd99cd4b07 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 31 Mar 2022 13:27:47 +0800 Subject: mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver Because mxs_nand_spl driver does not support DM, to use the minimum ECC layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC. Signed-off-by: Ye Li Reviewed-by: Han Xu --- drivers/mtd/nand/raw/mxs_nand.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index ee5d7fd..0c4e559 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1380,6 +1380,9 @@ int mxs_nand_init_spl(struct nand_chip *nand) else nand_info->max_ecc_strength_supported = 40; + if (IS_ENABLED(CONFIG_NAND_MXS_USE_MINIMUM_ECC)) + nand_info->use_minimum_ecc = true; + err = mxs_nand_alloc_buffers(nand_info); if (err) return err; -- cgit v1.1 From 0c45c77b8aeac0c3c5a0b5ea13a44ee478b51fdb Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Fri, 15 Apr 2022 16:40:49 +0530 Subject: i.MX6SX: crypto/fsl: fix entropy delay value RNG Hardware error is reported due to incorrect entropy delay rng self test are run to determine the correct ent_dly. test is executed with different voltage and temperature to identify the worst case value for ent_dly. after adding a margin value(1000), ent_dly should be at least 12000. Signed-off-by: Gaurav Jain Reviewed-by: Fabio Estevam --- drivers/crypto/fsl/jr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 1d951cf..85a3dac 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -623,7 +623,7 @@ static void kick_trng(int ent_delay, ccsr_sec_t *sec) static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) { - int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; + int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY; struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 inst_handles; @@ -652,6 +652,15 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) * the RNG. */ ret = instantiate_rng(sec_idx, sec, gen_sk); + /* + * entropy delay is calculated via self-test method. + * self-test are run across different volatge, temp. + * if worst case value for ent_dly is identified, + * loop can be skipped for that platform. + */ + if (IS_ENABLED(CONFIG_MX6SX)) + break; + } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); if (ret) { printf("SEC%u: Failed to instantiate RNG\n", sec_idx); -- cgit v1.1 From db74ced5dffc438924ac6ef2780bdb53cab50334 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Fri, 22 Apr 2022 16:38:34 +0530 Subject: i.MX8 crypto/fsl: Enable fsl CAAM rng driver rng driver enabled to read random number using caam. Signed-off-by: Gaurav Jain --- drivers/crypto/fsl/jr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 85a3dac..acd2992 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -767,8 +767,14 @@ init: return -1; } #if CONFIG_IS_ENABLED(OF_CONTROL) - if (ofnode_valid(scu_node)) + if (ofnode_valid(scu_node)) { + if (IS_ENABLED(CONFIG_DM_RNG)) { + ret = device_bind_driver(NULL, "caam-rng", "caam-rng", NULL); + if (ret) + printf("Couldn't bind rng driver (%d)\n", ret); + } return ret; + } #endif #ifdef CONFIG_FSL_CORENET -- cgit v1.1 From 290ffe57886271a6ac6b7750f70410ee51727f42 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Mon, 25 Apr 2022 16:22:48 +0200 Subject: imx8m: fix reading of DDR4 MR registers I was trying to employ lpddr4_mr_read() to something similar to what the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c differs from the private one used by that board in how it extracts the byte value, and I was only getting zeroes. Adding a bit of debug printf'ing gives me tmp = 0x00ffff00 tmp = 0x00070700 tmp = 0x00000000 tmp = 0x00101000 and indeed I was expecting a (combined) value of 0xff070010 (0xff being Manufacturer ID for Micron). I can't find any documentation that says how the values are supposed to be read, but clearly the iot-gate definition is the right one, both for its use case as well as my imx8mp-based board. So lift the private definition of lpddr4_mr_read() from the imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration in the ddr.h header where e.g. get_trained_CDD() is already declared. This has only been compile-tested for the imx8mm-cl-iot-gate board (since I don't have the hardware), but since I've merely moved its definition of lpddr4_mr_read(), I'd be surprised if it changed anything for that board. Signed-off-by: Rasmus Villemoes Tested-by: Ying-Chun Liu (PaulLiu) Reviewed-by: Fabio Estevam --- drivers/ddr/imx/imx8m/ddrphy_utils.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index a54449e..975d553 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -198,9 +198,14 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); } while ((tmp & 0x8) == 0); tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); - tmp = tmp & 0xff; reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); - + while (tmp) { //try to find a significant byte in the word + if (tmp & 0xff) { + tmp &= 0xff; + break; + } + tmp >>= 8; + } return tmp; } -- cgit v1.1 From cad77280c31f6736e93bf18060080fee50cc9ee3 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Wed, 11 May 2022 14:07:55 +0530 Subject: i.MX8ULP: add display_ele_fw_version api implement get f/w version api. print ele f/w version in spl. Signed-off-by: Gaurav Jain Reviewed-by: Peng Fan Reviewed-by: Pankaj Gupta --- drivers/misc/imx8ulp/s400_api.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'drivers') diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c index 3ffdeb2..87f5880 100644 --- a/drivers/misc/imx8ulp/s400_api.c +++ b/drivers/misc/imx8ulp/s400_api.c @@ -272,6 +272,47 @@ int ahab_release_caam(u32 core_did, u32 *response) return ret; } +int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct imx8ulp_s400_msg); + struct imx8ulp_s400_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + if (!fw_version) { + printf("Invalid parameters for f/w version read\n"); + return -EINVAL; + } + + if (!sha1) { + printf("Invalid parameters for commit sha1\n"); + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = AHAB_GET_FW_VERSION_CID; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + *fw_version = msg.data[1]; + *sha1 = msg.data[2]; + + return ret; +} + int ahab_dump_buffer(u32 *buffer, u32 buffer_length) { struct udevice *dev = gd->arch.s400_dev; -- cgit v1.1 From 1919f58a8f371c19c340127b6a76859867e90247 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Wed, 11 May 2022 14:23:19 +0530 Subject: crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish HW accelerated hash operations are giving incorrect hash output. so add flush and invalidate for input/output hash buffers. Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware acceleration.) Signed-off-by: Gaurav Jain --- drivers/crypto/fsl/fsl_hash.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index a52c4ac..9e6829b 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -149,12 +149,20 @@ static int caam_hash_finish(void *hash_ctx, void *dest_buf, driver_hash[caam_algo].digestsize, 1); + flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len); + flush_dcache_range((ulong)ctx->sha_desc, + (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE)); + flush_dcache_range((ulong)ctx->hash, + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize); + ret = run_descriptor_jr(ctx->sha_desc); if (ret) { debug("Error %x\n", ret); return ret; } else { + invalidate_dcache_range((ulong)ctx->hash, + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize); memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); } free(ctx); -- cgit v1.1 From 78bf8e802c33883d1069f165d95866d9b5cd36fc Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Sun, 15 May 2022 11:35:30 +0200 Subject: nand: raw: mxs_nand: Fix specific hook registration Move the hook after nand_scan_tail is called. The hook must be replaced to the mxs specific one but those must to be assignment later in the probe function. With this fix markbad is working again. Before this change: nand markbad 0xDEC00 NXS NAND: Writing OOB isn't supported NXS NAND: Writing OOB isn't supported block 0x000dec00 NOT marked as bad! ERROR 0 Cc: Han Xu Cc: Fabio Estevam Acked-by: Han Xu Tested-By: Tim Harvey Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/mxs_nand.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 0c4e559..7893e9d 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1246,22 +1246,6 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) /* Enable BCH complete interrupt */ writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set); - /* Hook some operations at the MTD level. */ - if (mtd->_read_oob != mxs_nand_hook_read_oob) { - nand_info->hooked_read_oob = mtd->_read_oob; - mtd->_read_oob = mxs_nand_hook_read_oob; - } - - if (mtd->_write_oob != mxs_nand_hook_write_oob) { - nand_info->hooked_write_oob = mtd->_write_oob; - mtd->_write_oob = mxs_nand_hook_write_oob; - } - - if (mtd->_block_markbad != mxs_nand_hook_block_markbad) { - nand_info->hooked_block_markbad = mtd->_block_markbad; - mtd->_block_markbad = mxs_nand_hook_block_markbad; - } - return 0; } @@ -1470,6 +1454,22 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) if (err) goto err_free_buffers; + /* Hook some operations at the MTD level. */ + if (mtd->_read_oob != mxs_nand_hook_read_oob) { + nand_info->hooked_read_oob = mtd->_read_oob; + mtd->_read_oob = mxs_nand_hook_read_oob; + } + + if (mtd->_write_oob != mxs_nand_hook_write_oob) { + nand_info->hooked_write_oob = mtd->_write_oob; + mtd->_write_oob = mxs_nand_hook_write_oob; + } + + if (mtd->_block_markbad != mxs_nand_hook_block_markbad) { + nand_info->hooked_block_markbad = mtd->_block_markbad; + mtd->_block_markbad = mxs_nand_hook_block_markbad; + } + err = nand_register(0, mtd); if (err) goto err_free_buffers; -- cgit v1.1 From a222c14792f15582648d1a00cdc40355ca9393ef Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Sun, 15 May 2022 11:35:31 +0200 Subject: mtd: nand: mxs_nand_spl: Fix bad block skipping The specific implementation was having bug. Those bugs are since the beginning of the implementation. Some manufactures can already experience this bug in their SPL code. This bug can be more visible on architecture that has complicated boot process like imx8mn. Older version of uboot can be affected if the bad block appear in correspoding of the beginning of u-boot image. In order to adjust the function we scan from the first erase block. The problematic part of old code was in this part: while (is_badblock(mtd, offs, 1)) { page = page + nand_page_per_block; /* Check i we've reached the end of flash. */ if (page >= mtd->size >> chip->page_shift) { free(page_buf); return -ENOMEM; } } Even we fix it adding increment of the offset of one erase block size , we don't fix the problem, because the first erase block where the image start is not checked. The code was tested on an imx8mn where the boot rom api was not able to skip it. This code is used by other architecures like imx6 and imx8mm Cc: Han Xu Cc: Fabio Estevam Acked-by: Han Xu Tested-By: Tim Harvey Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/mxs_nand_spl.c | 90 ++++++++++++++++++++----------------- 1 file changed, 49 insertions(+), 41 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 59a67ee..2bfb181 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -218,14 +218,14 @@ void nand_init(void) mxs_nand_setup_ecc(mtd); } -int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) { - struct nand_chip *chip; - unsigned int page; + unsigned int sz; + unsigned int block, lastblock; + unsigned int page, page_offset; unsigned int nand_page_per_block; - unsigned int sz = 0; + struct nand_chip *chip; u8 *page_buf = NULL; - u32 page_off; chip = mtd_to_nand(mtd); if (!chip->numchips) @@ -235,47 +235,42 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) if (!page_buf) return -ENOMEM; - page = offs >> chip->page_shift; - page_off = offs & (mtd->writesize - 1); + /* offs has to be aligned to a page address! */ + block = offs / mtd->erasesize; + lastblock = (offs + size - 1) / mtd->erasesize; + page = (offs % mtd->erasesize) / mtd->writesize; + page_offset = offs % mtd->writesize; nand_page_per_block = mtd->erasesize / mtd->writesize; - debug("%s offset:0x%08x len:%d page:%x\n", __func__, offs, size, page); - - while (size) { - if (mxs_read_page_ecc(mtd, page_buf, page) < 0) - return -1; - - if (size > (mtd->writesize - page_off)) - sz = (mtd->writesize - page_off); - else - sz = size; - - memcpy(buf, page_buf + page_off, sz); - - offs += mtd->writesize; - page++; - buf += (mtd->writesize - page_off); - page_off = 0; - size -= sz; - - /* - * Check if we have crossed a block boundary, and if so - * check for bad block. - */ - if (!(page % nand_page_per_block)) { - /* - * Yes, new block. See if this block is good. If not, - * loop until we find a good block. - */ - while (is_badblock(mtd, offs, 1)) { - page = page + nand_page_per_block; - /* Check i we've reached the end of flash. */ - if (page >= mtd->size >> chip->page_shift) { + while (block <= lastblock && size > 0) { + if (!is_badblock(mtd, mtd->erasesize * block, 1)) { + /* Skip bad blocks */ + while (page < nand_page_per_block) { + int curr_page = nand_page_per_block * block + page; + + if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) { free(page_buf); - return -ENOMEM; + return -EIO; } + + if (size > (mtd->writesize - page_offset)) + sz = (mtd->writesize - page_offset); + else + sz = size; + + memcpy(dst, page_buf + page_offset, sz); + dst += sz; + size -= sz; + page_offset = 0; + page++; } + + page = 0; + } else { + lastblock++; } + + block++; } free(page_buf); @@ -294,6 +289,19 @@ void nand_deselect(void) u32 nand_spl_adjust_offset(u32 sector, u32 offs) { - /* Handle the offset adjust in nand_spl_load_image,*/ + unsigned int block, lastblock; + + block = sector / mtd->erasesize; + lastblock = (sector + offs) / mtd->erasesize; + + while (block <= lastblock) { + if (is_badblock(mtd, block * mtd->erasesize, 1)) { + offs += mtd->erasesize; + lastblock++; + } + + block++; + } + return offs; } -- cgit v1.1 From 1d51e779e3f93af75516ddffd71323a503ba9fbf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 20 May 2022 05:10:16 +0200 Subject: pmic: pca9450: Add upstream regulators subnode match The upstream DT regulators node subnodes are named BUCKn and LDOn, the downstream DT regulators node subnodes are named buckn and ldon, add the upstream match. Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic --- drivers/power/pmic/pca9450.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 2394b19..26c876c 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "B", .driver = PCA9450_REGULATOR_DRIVER}, /* ldo */ { .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "L", .driver = PCA9450_REGULATOR_DRIVER}, { }, }; -- cgit v1.1 From 326337fb005f968911d897867d09d1228b070d84 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 20 May 2022 05:10:17 +0200 Subject: pmic: pca9450: Add regulator driver Add PCA9450 regulator driver. This is complementary driver for the BUCKn and LDOn regulators provided by the PCA9450 PMIC driver. Currently the driver permits reading the settngs and configuring the BUCKn and LDOn regulators. Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic --- drivers/power/pmic/pca9450.c | 6 +- drivers/power/regulator/Kconfig | 15 ++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/pca9450.c | 333 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 352 insertions(+), 3 deletions(-) create mode 100644 drivers/power/regulator/pca9450.c (limited to 'drivers') diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 26c876c..116ac49 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -83,9 +83,9 @@ static struct dm_pmic_ops pca9450_ops = { }; static const struct udevice_id pca9450_ids[] = { - { .compatible = "nxp,pca9450a", .data = 0x25, }, - { .compatible = "nxp,pca9450b", .data = 0x25, }, - { .compatible = "nxp,pca9450c", .data = 0x25, }, + { .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, }, + { .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, }, + { .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, }, { } }; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 9145408..d6cea8e 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -60,6 +60,21 @@ config SPL_DM_REGULATOR_BD71837 This config enables implementation of driver-model regulator uclass features for regulators on ROHM BD71837 and BD71847 in SPL. +config DM_REGULATOR_PCA9450 + bool "Enable Driver Model for NXP PCA9450 regulators" + depends on DM_REGULATOR && DM_PMIC_PCA9450 + help + This config enables implementation of driver-model regulator uclass + features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks + and 5 LDOS. The driver implements get/set api for value and enable. + +config SPL_DM_REGULATOR_PCA9450 + bool "Enable Driver Model for NXP PCA9450 regulators in SPL" + depends on DM_REGULATOR_PCA9450 + help + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM PCA9450 in SPL. + config DM_REGULATOR_DA9063 bool "Enable Driver Model for REGULATOR DA9063" depends on DM_REGULATOR && DM_PMIC_DA9063 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index b9883df..bc73606 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_PCA9450) += pca9450.o obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c new file mode 100644 index 0000000..23badaa --- /dev/null +++ b/drivers/power/regulator/pca9450.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * NXP PCA9450 regulator driver + * Copyright (C) 2022 Marek Vasut + * + * Largely based on: + * ROHM BD71837 regulator driver + */ + +#include +#include +#include +#include +#include +#include +#include + +#define HW_STATE_CONTROL 0 +#define DEBUG + +/** + * struct pca9450_vrange - describe linear range of voltages + * + * @min_volt: smallest voltage in range + * @step: how much voltage changes at each selector step + * @min_sel: smallest selector in the range + * @max_sel: maximum selector in the range + */ +struct pca9450_vrange { + unsigned int min_volt; + unsigned int step; + u8 min_sel; + u8 max_sel; +}; + +/** + * struct pca9450_plat - describe regulator control registers + * + * @name: name of the regulator. Used for matching the dt-entry + * @enable_reg: register address used to enable/disable regulator + * @enablemask: register mask used to enable/disable regulator + * @volt_reg: register address used to configure regulator voltage + * @volt_mask: register mask used to configure regulator voltage + * @ranges: pointer to ranges of regulator voltages and matching register + * values + * @numranges: number of voltage ranges pointed by ranges + * @dvs: whether the voltage can be changed when regulator is enabled + */ +struct pca9450_plat { + const char *name; + u8 enable_reg; + u8 enablemask; + u8 volt_reg; + u8 volt_mask; + struct pca9450_vrange *ranges; + unsigned int numranges; + bool dvs; +}; + +#define PCA_RANGE(_min, _vstep, _sel_low, _sel_hi) \ +{ \ + .min_volt = (_min), .step = (_vstep), \ + .min_sel = (_sel_low), .max_sel = (_sel_hi), \ +} + +#define PCA_DATA(_name, enreg, enmask, vreg, vmask, _range, _dvs) \ +{ \ + .name = (_name), .enable_reg = (enreg), .enablemask = (enmask), \ + .volt_reg = (vreg), .volt_mask = (vmask), .ranges = (_range), \ + .numranges = ARRAY_SIZE(_range), .dvs = (_dvs), \ +} + +static struct pca9450_vrange pca9450_buck123_vranges[] = { + PCA_RANGE(600000, 12500, 0, 0x7f), +}; + +static struct pca9450_vrange pca9450_buck456_vranges[] = { + PCA_RANGE(600000, 25000, 0, 0x70), + PCA_RANGE(3400000, 0, 0x71, 0x7f), +}; + +static struct pca9450_vrange pca9450_ldo1_vranges[] = { + PCA_RANGE(1600000, 100000, 0x0, 0x3), + PCA_RANGE(3000000, 100000, 0x4, 0x7), +}; + +static struct pca9450_vrange pca9450_ldo2_vranges[] = { + PCA_RANGE(800000, 50000, 0x0, 0x7), +}; + +static struct pca9450_vrange pca9450_ldo34_vranges[] = { + PCA_RANGE(800000, 100000, 0x0, 0x19), + PCA_RANGE(3300000, 0, 0x1a, 0x1f), +}; + +static struct pca9450_vrange pca9450_ldo5_vranges[] = { + PCA_RANGE(1800000, 100000, 0x0, 0xf), +}; + +/* + * We use enable mask 'HW_STATE_CONTROL' to indicate that this regulator + * must not be enabled or disabled by SW. The typical use-case for PCA9450 + * is powering NXP i.MX8. In this use-case we (for now) only allow control + * for BUCK4, BUCK5, BUCK6 which are not boot critical. + */ +static struct pca9450_plat pca9450_reg_data[] = { + /* Bucks 1-3 which support dynamic voltage scaling */ + PCA_DATA("BUCK1", PCA9450_BUCK1CTRL, HW_STATE_CONTROL, + PCA9450_BUCK1OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_buck123_vranges, true), + PCA_DATA("BUCK2", PCA9450_BUCK2CTRL, HW_STATE_CONTROL, + PCA9450_BUCK2OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_buck123_vranges, true), + PCA_DATA("BUCK3", PCA9450_BUCK3CTRL, HW_STATE_CONTROL, + PCA9450_BUCK3OUT_DVS0, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_buck123_vranges, true), + /* Bucks 4-6 which do not support dynamic voltage scaling */ + PCA_DATA("BUCK4", PCA9450_BUCK4CTRL, HW_STATE_CONTROL, + PCA9450_BUCK4OUT, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_buck456_vranges, false), + PCA_DATA("BUCK5", PCA9450_BUCK5CTRL, HW_STATE_CONTROL, + PCA9450_BUCK5OUT, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_buck456_vranges, false), + PCA_DATA("BUCK6", PCA9450_BUCK6CTRL, HW_STATE_CONTROL, + PCA9450_BUCK6OUT, PCA9450_DVS_BUCK_RUN_MASK, + pca9450_buck456_vranges, false), + /* LDOs */ + PCA_DATA("LDO1", PCA9450_LDO1CTRL, HW_STATE_CONTROL, + PCA9450_LDO1CTRL, PCA9450_LDO12_MASK, + pca9450_ldo1_vranges, false), + PCA_DATA("LDO2", PCA9450_LDO2CTRL, HW_STATE_CONTROL, + PCA9450_LDO2CTRL, PCA9450_LDO12_MASK, + pca9450_ldo2_vranges, false), + PCA_DATA("LDO3", PCA9450_LDO3CTRL, HW_STATE_CONTROL, + PCA9450_LDO3CTRL, PCA9450_LDO34_MASK, + pca9450_ldo34_vranges, false), + PCA_DATA("LDO4", PCA9450_LDO4CTRL, HW_STATE_CONTROL, + PCA9450_LDO4CTRL, PCA9450_LDO34_MASK, + pca9450_ldo34_vranges, false), + PCA_DATA("LDO5", PCA9450_LDO5CTRL_H, HW_STATE_CONTROL, + PCA9450_LDO5CTRL_H, PCA9450_LDO5_MASK, + pca9450_ldo5_vranges, false), +}; + +static int vrange_find_value(struct pca9450_vrange *r, unsigned int sel, + unsigned int *val) +{ + if (!val || sel < r->min_sel || sel > r->max_sel) + return -EINVAL; + + *val = r->min_volt + r->step * (sel - r->min_sel); + return 0; +} + +static int vrange_find_selector(struct pca9450_vrange *r, int val, + unsigned int *sel) +{ + int ret = -EINVAL; + int num_vals = r->max_sel - r->min_sel + 1; + + if (val >= r->min_volt && + val <= r->min_volt + r->step * (num_vals - 1)) { + if (r->step) { + *sel = r->min_sel + ((val - r->min_volt) / r->step); + ret = 0; + } else { + *sel = r->min_sel; + ret = 0; + } + } + return ret; +} + +static int pca9450_get_enable(struct udevice *dev) +{ + struct pca9450_plat *plat = dev_get_plat(dev); + int val; + + /* + * boot critical regulators on pca9450 must not be controlled by sw + * due to the 'feature' which leaves power rails down if pca9450 is + * reseted to snvs state. hence we can't get the state here. + * + * if we are alive it means we probably are on run state and + * if the regulator can't be controlled we can assume it is + * enabled. + */ + if (plat->enablemask == HW_STATE_CONTROL) + return 1; + + val = pmic_reg_read(dev->parent, plat->enable_reg); + if (val < 0) + return val; + + return (val & plat->enablemask); +} + +static int pca9450_set_enable(struct udevice *dev, bool enable) +{ + int val = 0; + struct pca9450_plat *plat = dev_get_plat(dev); + + /* + * boot critical regulators on pca9450 must not be controlled by sw + * due to the 'feature' which leaves power rails down if pca9450 is + * reseted to snvs state. Hence we can't set the state here. + */ + if (plat->enablemask == HW_STATE_CONTROL) + return enable ? 0 : -EINVAL; + + if (enable) + val = plat->enablemask; + + return pmic_clrsetbits(dev->parent, plat->enable_reg, plat->enablemask, + val); +} + +static int pca9450_get_value(struct udevice *dev) +{ + struct pca9450_plat *plat = dev_get_plat(dev); + unsigned int reg, tmp; + int i, ret; + + ret = pmic_reg_read(dev->parent, plat->volt_reg); + if (ret < 0) + return ret; + + reg = ret; + reg &= plat->volt_mask; + + for (i = 0; i < plat->numranges; i++) { + struct pca9450_vrange *r = &plat->ranges[i]; + + if (!vrange_find_value(r, reg, &tmp)) + return tmp; + } + + pr_err("Unknown voltage value read from pmic\n"); + + return -EINVAL; +} + +static int pca9450_set_value(struct udevice *dev, int uvolt) +{ + struct pca9450_plat *plat = dev_get_plat(dev); + unsigned int sel; + int i, found = 0; + + /* + * An under/overshooting may occur if voltage is changed for other + * regulators but buck 1,2,3 or 4 when regulator is enabled. Prevent + * change to protect the HW + */ + if (!plat->dvs) + if (pca9450_get_enable(dev)) { + /* If the value is already set, skip the warning. */ + if (pca9450_get_value(dev) == uvolt) + return 0; + pr_err("Only DVS bucks can be changed when enabled\n"); + return -EINVAL; + } + + for (i = 0; i < plat->numranges; i++) { + struct pca9450_vrange *r = &plat->ranges[i]; + + found = !vrange_find_selector(r, uvolt, &sel); + if (found) { + unsigned int tmp; + + /* + * We require exactly the requested value to be + * supported - this can be changed later if needed + */ + found = !vrange_find_value(r, sel, &tmp); + if (found && tmp == uvolt) + break; + found = 0; + } + } + + if (!found) + return -EINVAL; + + return pmic_clrsetbits(dev->parent, plat->volt_reg, + plat->volt_mask, sel); +} + +static int pca9450_regulator_probe(struct udevice *dev) +{ + struct pca9450_plat *plat = dev_get_plat(dev); + int i, type; + + type = dev_get_driver_data(dev_get_parent(dev)); + + if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC) { + debug("Unknown PMIC type\n"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(pca9450_reg_data); i++) { + if (strcmp(dev->name, pca9450_reg_data[i].name)) + continue; + + /* PCA9450B/PCA9450C uses BUCK1 and BUCK3 in dual-phase */ + if (type == NXP_CHIP_TYPE_PCA9450BC && + !strcmp(pca9450_reg_data[i].name, "BUCK3")) { + continue; + } + + *plat = pca9450_reg_data[i]; + + return 0; + } + + pr_err("Unknown regulator '%s'\n", dev->name); + + return -ENOENT; +} + +static const struct dm_regulator_ops pca9450_regulator_ops = { + .get_value = pca9450_get_value, + .set_value = pca9450_set_value, + .get_enable = pca9450_get_enable, + .set_enable = pca9450_set_enable, +}; + +U_BOOT_DRIVER(pca9450_regulator) = { + .name = PCA9450_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &pca9450_regulator_ops, + .probe = pca9450_regulator_probe, + .plat_auto = sizeof(struct pca9450_plat), +}; -- cgit v1.1 From 0539d16d22f65b5958800489701249f990531073 Mon Sep 17 00:00:00 2001 From: Christoph Fritz Date: Tue, 5 Apr 2022 12:29:30 +0200 Subject: gpio: rgpio2p: Enhance reading of GPIO pin value Add support for reading GPIO pin value when function is output. With this patch applied, gpio toggle command is working. Signed-off-by: Christoph Fritz Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam --- drivers/gpio/imx_rgpio2p.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 0e2874c..175e460 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -39,6 +39,14 @@ static int imx_rgpio2p_is_output(struct gpio_regs *regs, int offset) return val & (1 << offset) ? 1 : 0; } +static int imx_rgpio2p_bank_get_direction(struct gpio_regs *regs, int offset) +{ + if ((readl(®s->gpio_pddr) >> offset) & 0x01) + return IMX_RGPIO2P_DIRECTION_OUT; + + return IMX_RGPIO2P_DIRECTION_IN; +} + static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset, enum imx_rgpio2p_direction direction) { @@ -67,7 +75,11 @@ static void imx_rgpio2p_bank_set_value(struct gpio_regs *regs, int offset, static int imx_rgpio2p_bank_get_value(struct gpio_regs *regs, int offset) { - return (readl(®s->gpio_pdir) >> offset) & 0x01; + if (imx_rgpio2p_bank_get_direction(regs, offset) == + IMX_RGPIO2P_DIRECTION_IN) + return (readl(®s->gpio_pdir) >> offset) & 0x01; + + return (readl(®s->gpio_pdor) >> offset) & 0x01; } static int imx_rgpio2p_direction_input(struct udevice *dev, unsigned offset) -- cgit v1.1