From e90d2659e46ab9483c24e08611c06922a8ec25d4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jun 2018 09:43:34 +0200 Subject: serial: zynq: Write chars till output fifo is full Change logic and put char to fifo till there is a space in output fifo. Origin logic was that output fifo needs to be empty. It means only one char was in output queue. Also remove unused ZYNQ_UART_SR_TXEMPTY macro. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/serial/serial_zynq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/serial') diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 7a6f822..4ae2493 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -15,8 +15,8 @@ #include #include -#define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */ #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ +#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ @@ -93,7 +93,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) return -EAGAIN; writel(c, ®s->tx_rx_fifo); -- cgit v1.1