From 8097aee3abc3b773aceea01f756a38b34b274e1e Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Fri, 6 Dec 2019 13:47:32 -0600 Subject: ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer Reviewed-by: Ley Foon Tan --- drivers/ddr/altera/sdram_agilex.c | 6 +++--- drivers/ddr/altera/sdram_s10.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/ddr') diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index cc7679a..0cbcd14 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -143,9 +143,6 @@ int sdram_mmr_init_full(struct udevice *dev) setbits_le32(plat->hmc + ERRINTEN, DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK); - /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ - writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); - if (!cpu_has_been_warmreset()) sdram_init_ecc_bits(&bd); } else { @@ -158,6 +155,9 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } + /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + sdram_size_check(&bd); priv->info.base = bd.bi_dram[0].start; diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index cf586ac..93c15dd 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -307,9 +307,6 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS); - /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ - writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); - /* Initialize memory content if not from warm reset */ if (!cpu_has_been_warmreset()) sdram_init_ecc_bits(&bd); @@ -323,6 +320,9 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } + /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + sdram_size_check(&bd); priv->info.base = bd.bi_dram[0].start; -- cgit v1.1