From f303aaf21b968ab959edcc354892f9eca8907e0b Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Tue, 18 Jul 2017 17:37:27 +0200
Subject: ram: stm32: add second SDRAM bank management

FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 doc/device-tree-bindings/ram/st,stm32-fmc.txt | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

(limited to 'doc')

diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt
index 3d1392c..99f76d5 100644
--- a/doc/device-tree-bindings/ram/st,stm32-fmc.txt
+++ b/doc/device-tree-bindings/ram/st,stm32-fmc.txt
@@ -40,12 +40,19 @@ Example:
 		pinctrl-names = "default";
 		status = "okay";
 
-		mr-nbanks = <1>;
 		/* sdram memory configuration from sdram datasheet */
-	bank1: bank@0 {
-	       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+		bank1: bank@0 {
+		       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
 						CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
-	       st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+		       st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
 						TRCD_18>;
-       };
-}
+		};
+
+		/* sdram memory configuration from sdram datasheet */
+		bank2: bank@1 {
+		       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+						CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
+		       st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+						TRCD_18>;
+		};
+	}
-- 
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