From 887e2ec9ecf49366a60a49b32b73825804909865 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 7 Sep 2006 11:51:23 +0200 Subject: Add support for AMCC Sequoia PPC440EPx eval board - Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006 --- doc/README.nand-boot-ppc440 | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 doc/README.nand-boot-ppc440 (limited to 'doc') diff --git a/doc/README.nand-boot-ppc440 b/doc/README.nand-boot-ppc440 new file mode 100644 index 0000000..a82a10e --- /dev/null +++ b/doc/README.nand-boot-ppc440 @@ -0,0 +1,36 @@ +----------------------------- +NAND boot on PPC440 platforms +----------------------------- + +This document describes the U-Boot NAND boot feature as it +is implemented for the AMCC Sequoia (PPC440EPx) board. + +The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH, +completely without NOR FLASH. This can be done by using the NAND +boot feature of the 440 NAND flash controller (NDFC). + +Here a short desciption of the different boot stages: + +a) IPL (Initial Program Loader, integrated inside CPU) +------------------------------------------------------ +Will load first 4k from NAND (SPL) into cache and execute it from there. + +b) SPL (Secondary Program Loader) +--------------------------------- +Will load special U-Boot version (NUB) from NAND and execute it. This SPL +has to fit into 4kByte. It sets up the CPU and configures the SDRAM +controller and the NAND controller so that the special U-Boot image can be +loaded from NAND to SDRAM. +This special image is build in the directory "nand_spl". + +c) NUB (NAND U-Boot) +-------------------- +This NAND U-Boot (NUB) is a special U-Boot version which can be started +from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + +On 440EPx the SPL is copied to internal SRAM before the NAND controller +is set up. While still running from cache, I experienced problems accessing +the NAND controller. + + +September 07 2006, Stefan Roese -- cgit v1.1 From a73c8dbb437fb55ecb660cb962c8c1cc85b8a654 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 12 Sep 2006 08:49:07 +0200 Subject: Update NAND boot documentation Patch by Stefan Roese, 12 Sep 2006 --- doc/README.nand-boot-ppc440 | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'doc') diff --git a/doc/README.nand-boot-ppc440 b/doc/README.nand-boot-ppc440 index a82a10e..a1c1d8c 100644 --- a/doc/README.nand-boot-ppc440 +++ b/doc/README.nand-boot-ppc440 @@ -33,4 +33,28 @@ is set up. While still running from cache, I experienced problems accessing the NAND controller. +Example: Build and install NAND boot image for Sequoia (440EPx): + +a) Configure for sequoia with NAND boot support: +# make sequoia_nand_config + +b) Build image(s) +# make + +This will generate the SPL image in the "nand_spl" directory: +nand_spl/u-boot-spl.bin +Also another image is created spanning a whole NAND block (16kBytes): +nand_spl/u-boot-spl-16k.bin +The main NAND U-Boot image is generated in the toplevel directory: +u-boot.bin +A combined image of u-boot-spl-16k.bin and u-boot.bin is also created: +u-boot-nand.bin + +This image should be programmed at offset 0 in the NAND flash: + +# tftp 100000 /tftpboot/sequoia/u-boot-nand.bin +# nand erase 0 60000 +# nand write 100000 0 60000 + + September 07 2006, Stefan Roese -- cgit v1.1