From 344eb6d572adfadb0a11196ef8cf6508f6c704df Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 14 Feb 2020 11:18:15 +0200 Subject: misc: k3_esm: Add support for Texas Instruments K3 ESM driver The ESM (Error Signaling Module) is used to route error signals within the K3 SoCs somewhat similar to interrupts. The handling for these is different though, and can be routed for hardware error handling, to be handled by safety processor or just as error interrupts handled by the main processor. The u-boot level ESM driver is just used to configure the ESM signals so that they get routed to proper destination. Signed-off-by: Tero Kristo --- doc/device-tree-bindings/misc/esm-k3.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 doc/device-tree-bindings/misc/esm-k3.txt (limited to 'doc') diff --git a/doc/device-tree-bindings/misc/esm-k3.txt b/doc/device-tree-bindings/misc/esm-k3.txt new file mode 100644 index 0000000..01c8b6b --- /dev/null +++ b/doc/device-tree-bindings/misc/esm-k3.txt @@ -0,0 +1,25 @@ +Texas Instruments K3 ESM Binding +====================== + +ESM (Error Signaling Module) is an IP block on TI K3 devices that allows +handling of safety events somewhat similar to what interrupt controller +would do. The safety signals have their separate paths within the SoC, +and they are handled by the ESM, which routes them to the proper +destination, which can be system reset, interrupt controller, etc. In +the simplest configuration the signals are just routed to reset the +SoC. + +Required properties : +- compatible : "ti,j721e-esm" +- ti,esm-pins : integer array of esm events IDs to route to external event + pin which can be used to reset the SoC. The array can + have arbitrary amount of event IDs listed on it. + +Example +======= + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; -- cgit v1.1 From 3b36b38f50cc3063f922db629f529b11ff92332b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 14 Feb 2020 11:18:16 +0200 Subject: misc: pmic_esm: Add support for PMIC ESM driver The ESM (Error Signal Monitor) is used on certain PMIC versions to handle error signals propagating from rest of the system. If these reach the PMIC, it is typically a last resort fatal error which requires a system reset. The ESM driver does the proper configuration for the ESM module to reach this end goal. Initially, only TPS65941 PMIC is supported for this. Signed-off-by: Tero Kristo --- doc/device-tree-bindings/misc/esm-pmic.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 doc/device-tree-bindings/misc/esm-pmic.txt (limited to 'doc') diff --git a/doc/device-tree-bindings/misc/esm-pmic.txt b/doc/device-tree-bindings/misc/esm-pmic.txt new file mode 100644 index 0000000..a60ad74 --- /dev/null +++ b/doc/device-tree-bindings/misc/esm-pmic.txt @@ -0,0 +1,19 @@ +PMIC ESM Binding +====================== + +Certain Power Management ICs contain safety handling logic within them, +allowing automatic reset of the board in case a safety error is signaled. +For this purpose, ESM (Error Signal Monitor) is implemented within +the PMIC running its own state machine. + +Required properties : +- compatible : "ti,tps659413-esm" + +Example +======= + +&tps659413a { + esm: esm { + compatible = "ti,tps659413-esm"; + }; +}; -- cgit v1.1 From cb8680a4b84a2df5897a1870db09054e2217500f Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 22 Feb 2020 14:05:47 +0100 Subject: fdt: video: omap: add framebuffer and panel bindings Add device-tree binding documentation for ti framebuffer and generic panel output driver. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- doc/device-tree-bindings/video/tilcdc/panel.txt | 66 +++++++++++++++++++ doc/device-tree-bindings/video/tilcdc/tilcdc.txt | 82 ++++++++++++++++++++++++ 2 files changed, 148 insertions(+) create mode 100644 doc/device-tree-bindings/video/tilcdc/panel.txt create mode 100644 doc/device-tree-bindings/video/tilcdc/tilcdc.txt (limited to 'doc') diff --git a/doc/device-tree-bindings/video/tilcdc/panel.txt b/doc/device-tree-bindings/video/tilcdc/panel.txt new file mode 100644 index 0000000..8082163 --- /dev/null +++ b/doc/device-tree-bindings/video/tilcdc/panel.txt @@ -0,0 +1,66 @@ +Device-Tree bindings for tilcdc DRM generic panel output driver + +Required properties: + - compatible: value should be "ti,tilcdc,panel". + - panel-info: configuration info to configure LCDC correctly for the panel + - ac-bias: AC Bias Pin Frequency + - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt + - dma-burst-sz: DMA burst size + - bpp: Bits per pixel + - fdd: FIFO DMA Request Delay + - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling + - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore + - raster-order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most + - fifo-th: DMA FIFO threshold + - display-timings: typical videomode of lcd panel. Multiple video modes + can be listed if the panel supports multiple timings, but the 'native-mode' + should be the preferred/default resolution. Refer to + Documentation/devicetree/bindings/display/panel/display-timing.txt for display + timing binding details. + +Optional properties: +- backlight: phandle of the backlight device attached to the panel +- enable-gpios: GPIO pin to enable or disable the panel + +Recommended properties: + - pinctrl-names, pinctrl-0: the pincontrol settings to configure + muxing properly for pins that connect to TFP410 device + +Example: + + /* Settings for CDTech_S035Q01 / LCD3 cape: */ + lcd3 { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&bone_lcd3_cape_lcd_pins>; + backlight = <&backlight>; + enable-gpios = <&gpio3 19 0>; + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + native-mode = <&timing0>; + timing0: 320x240 { + hactive = <320>; + vactive = <240>; + hback-porch = <21>; + hfront-porch = <58>; + hsync-len = <47>; + vback-porch = <11>; + vfront-porch = <23>; + vsync-len = <2>; + clock-frequency = <8000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; diff --git a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt new file mode 100644 index 0000000..7bf1bb4 --- /dev/null +++ b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt @@ -0,0 +1,82 @@ +Device-Tree bindings for tilcdc DRM driver + +Required properties: + - compatible: value should be one of the following: + - "ti,am33xx-tilcdc" for AM335x based boards + - "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards + - interrupts: the interrupt number + - reg: base address and size of the LCDC device + +Recommended properties: + - ti,hwmods: Name of the hwmod associated to the LCDC + +Optional properties: + - max-bandwidth: The maximum pixels per second that the memory + interface / lcd controller combination can sustain + - max-width: The maximum horizontal pixel width supported by + the lcd controller. + - max-pixelclock: The maximum pixel clock that can be supported + by the lcd controller in KHz. + - blue-and-red-wiring: Recognized values "straight" or "crossed". + This property deals with the LCDC revision 2 (found on AM335x) + color errata [1]. + - "straight" indicates normal wiring that supports RGB565, + BGR888, and XBGR8888 color formats. + - "crossed" indicates wiring that has blue and red wires + crossed. This setup supports BGR565, RGB888 and XRGB8888 + formats. + - If the property is not present or its value is not recognized + the legacy mode is assumed. This configuration supports RGB565, + RGB888 and XRGB8888 formats. However, depending on wiring, the red + and blue colors are swapped in either 16 or 24-bit color modes. + +Optional nodes: + + - port/ports: to describe a connection to an external encoder. The + binding follows Documentation/devicetree/bindings/graph.txt and + supports a single port with a single endpoint. + + - See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and + Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting + tfp410 DVI encoder or lcd panel to lcdc + +[1] There is an errata about AM335x color wiring. For 16-bit color mode + the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]), + but for 24 bit color modes the wiring of blue and red components is + crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is + for Blue[3-7]. For more details see section 3.1.1 in AM335x + Silicon Errata: + http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360 + +Example: + + fb: fb@4830e000 { + compatible = "ti,am33xx-tilcdc", "ti,da850-tilcdc"; + reg = <0x4830e000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <36>; + ti,hwmods = "lcdc"; + + blue-and-red-wiring = "crossed"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; + }; + + tda19988: tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + port { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; + }; -- cgit v1.1 From 092d9ea26cde419141d340fd5de16c32f7273e00 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Feb 2020 18:24:42 +0100 Subject: doc: i2c: gpio: Document deblock sequence on probe Document the gpio-i2c deblocking sequence binding. Signed-off-by: Marek Vasut Reviewed-by: Heiko Schocher --- doc/device-tree-bindings/i2c/i2c-gpio.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'doc') diff --git a/doc/device-tree-bindings/i2c/i2c-gpio.txt b/doc/device-tree-bindings/i2c/i2c-gpio.txt index ba56ed5..e29eeba 100644 --- a/doc/device-tree-bindings/i2c/i2c-gpio.txt +++ b/doc/device-tree-bindings/i2c/i2c-gpio.txt @@ -16,6 +16,8 @@ Optional: The resulting transfer speed can be adjusted by setting the delay[us] between gpio-toggle operations. Speed [Hz] = 1000000 / 4 * udelay[us], It not defined, then default is 5us (~50KHz). +* i2c-gpio,deblock + Run deblocking sequence when the driver gets probed. Example: -- cgit v1.1 From ba6fb2f6aca54c6555742d507290cbfaa655e623 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 16 Mar 2020 07:55:06 +0100 Subject: dm: i2c-gpio: add support for clock stretching This adds support for clock stretching to the i2c-gpio driver. This is accomplished by switching the GPIO used for the SCL line to an input when it should be driven high, and polling on the SCL line value until it goes high (indicating that the I2C slave is no longer pulling it low). This is enabled by default; for gpios which cannot be configured as inputs, the i2c-gpio,scl-output-only property can be used to fall back to the previous behavior. Signed-off-by: Michael Auchter Cc: Heiko Schocher Reviewed-by: Heiko Schocher --- doc/device-tree-bindings/i2c/i2c-gpio.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'doc') diff --git a/doc/device-tree-bindings/i2c/i2c-gpio.txt b/doc/device-tree-bindings/i2c/i2c-gpio.txt index e29eeba..b06b829 100644 --- a/doc/device-tree-bindings/i2c/i2c-gpio.txt +++ b/doc/device-tree-bindings/i2c/i2c-gpio.txt @@ -18,6 +18,8 @@ Optional: It not defined, then default is 5us (~50KHz). * i2c-gpio,deblock Run deblocking sequence when the driver gets probed. +* i2c-gpio,scl-output-only; + Set if SCL is an output only Example: -- cgit v1.1 From 80e8b8add057d2c947394d9d57fc2dcc7ff886d1 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 2 Mar 2020 15:43:59 +0100 Subject: bootcounter: add DM support for memory based bootcounter add DM/DTS support for the memory based bootcounter in drivers/bootcount/bootcount.c. Let the old implementation in, so boards which have not yet convert to DM/DTS do not break. Signed-off-by: Heiko Schocher Reviewed-by: Simon Glass --- doc/device-tree-bindings/misc/bootcounter.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 doc/device-tree-bindings/misc/bootcounter.txt (limited to 'doc') diff --git a/doc/device-tree-bindings/misc/bootcounter.txt b/doc/device-tree-bindings/misc/bootcounter.txt new file mode 100644 index 0000000..d32fbc3 --- /dev/null +++ b/doc/device-tree-bindings/misc/bootcounter.txt @@ -0,0 +1,21 @@ +U-Boot bootcounter Devicetree Binding +===================================== + +The device tree node describes the U-Boot bootcounter +memory based device binding. + +Required properties : + +- compatible : "u-boot,bootcount"; +- single-word : set this, if you have only one word space + for storing the bootcounter. + +Example +------- + +MPC83xx based board: + +bootcount@0x13ff8 { + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; +}; -- cgit v1.1 From 7ae22d72781de76b3c23b018a3fccc172e9875de Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 12 Feb 2020 19:37:38 +0100 Subject: arm: stm32mp: bsec: add permanent lock support in bsec driver Add BSEC lock access (read / write) at 0xC0000000 offset of misc driver. The write access only available for Trusted boot mode, based on new SMC STM32_SMC_WRLOCK_OTP. With the fuse command, the permanent lock status is accessed with 0x10000000 offset (0xC0000000 - 0x8000000 for OTP sense/program divided by u32 size), for example: Read lock status of fuse 57 (0x39) STM32MP> fuse sense 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 Set permanent lock of fuse 57 (0x39) STM32MP> fuse prog 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 WARNING: the OTP lock is updated only after reboot WARING: Programming lock or fuses is an irreversible operation! This may brick your system. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- doc/board/st/stm32mp1.rst | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) (limited to 'doc') diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 1640bf9..ee42af6 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -416,20 +416,26 @@ For STMicroelectonics board, it is retrieved in STM32MP15x OTP : - OTP_58[15:0] = MAC_ADDR[47:32] To program a MAC address on virgin OTP words above, you can use the fuse command -on bank 0 to access to internal OTP: +on bank 0 to access to internal OTP and lock them: Prerequisite: check if a MAC address isn't yet programmed in OTP -1) check OTP: their value must be equal to 0 +1) check OTP: their value must be equal to 0:: - STM32MP> fuse sense 0 57 2 - Sensing bank 0: - Word 0x00000039: 00000000 00000000 + STM32MP> fuse sense 0 57 2 + Sensing bank 0: + Word 0x00000039: 00000000 00000000 + +2) check environment variable:: + + STM32MP> env print ethaddr + ## Error: "ethaddr" not defined -2) check environment variable +3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 1=locked):: - STM32MP> env print ethaddr - ## Error: "ethaddr" not defined + STM32MP> fuse sense 0 0x10000039 2 + Sensing bank 0: + Word 0x10000039: 00000000 00000000 Example to set mac address "12:34:56:78:9a:bc" @@ -443,11 +449,19 @@ Example to set mac address "12:34:56:78:9a:bc" Sensing bank 0: Word 0x00000039: 78563412 0000bc9a -3) next REBOOT, in the trace:: +3) Lock OTP:: + + STM32MP> fuse prog 0 0x10000039 1 1 + + STM32MP> fuse sense 0 0x10000039 2 + Sensing bank 0: + Word 0x10000039: 00000001 00000001 + +4) next REBOOT, in the trace:: ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc" -4) check env update:: +5) check env update:: STM32MP> env print ethaddr ethaddr=12:34:56:78:9a:bc -- cgit v1.1 From 050fed8a974790f553b580f8e2cdb26181f875c1 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 26 Feb 2020 11:26:43 +0100 Subject: stm32mp1: add 800 MHz profile support The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A : Cortex-A7 @ 650 MHz - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D : Cortex-A7 @ 800 MHz - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- doc/board/st/stm32mp1.rst | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'doc') diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index ee42af6..b7a0fbf 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -25,6 +25,14 @@ It features: - Standard connectivity, widely inherited from the STM32 MCU family - Comprehensive security support +Each line comes with a security option (cryptography & secure boot) and +a Cortex-A frequency option: + + - A : Cortex-A7 @ 650 MHz + - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz + - D : Cortex-A7 @ 800 MHz + - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz + Everything is supported in Linux but U-Boot is limited to: 1. UART -- cgit v1.1 From 9368bdfebde16368cdb642adbb12f9c871c94d63 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 6 Mar 2020 11:14:11 +0100 Subject: ram: stm32mp1: the property st, phy-cal becomes optional This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'doc') diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt index ee708ce..ac6a7df 100644 --- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt +++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt @@ -129,6 +129,8 @@ phyc attributes: MR3 - st,phy-cal : phy cal depending of calibration or tuning of DDR + This parameter is optional; when it is absent the built-in PHY + calibration is done. for STM32MP15x: 12 values are requested in this order DX0DLLCR DX0DQTR -- cgit v1.1 From f7c6ee7fe7bcc387de4c92300f46cb725b845b53 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Feb 2020 15:03:29 +0100 Subject: ARM: zynq: Switch to single zynq configurations There are a lot of zynq configurations which can be merged together and use only one for all. The similar change has been done for ZynqMP by commit be1b6c32d940 ("arm64: zynqmp: Use zynqmp_virt platform") Build SPL with u-boot.img for zc706 like this. export DEVICE_TREE=zynq-zc706 && make xilinx_zynq_virt_defconfig && make -j8 u-boot.img is generic for all boards. Tested on Zybo, zc702, zc706, zc770-xm011-x16, cc108 and microzed. Signed-off-by: Michal Simek --- doc/board/xilinx/zynq.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/board/xilinx/zynq.rst b/doc/board/xilinx/zynq.rst index 3f0513e..6a09df1 100644 --- a/doc/board/xilinx/zynq.rst +++ b/doc/board/xilinx/zynq.rst @@ -32,7 +32,8 @@ Building configure and build for zc702 board:: - $ make zynq_zc702_config + $ export DEVICE_TREE=zynq-zc702 + $ make xilinx_zynq_virt_defconfig $ make Bootmode -- cgit v1.1 From a1f49ab6a1131131c3f7bf3df9af15593888d396 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 18 Mar 2020 09:42:39 -0600 Subject: sandbox: Add documentation about required/useful packages Quite a few packages are used by sandbox or tools. Add a list of these to help people setting up for the first time. Signed-off-by: Simon Glass --- doc/arch/sandbox.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'doc') diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst index e577a95..6a1c6fc 100644 --- a/doc/arch/sandbox.rst +++ b/doc/arch/sandbox.rst @@ -34,6 +34,16 @@ integers can only be built on 64-bit hosts. Note that standalone/API support is not available at present. +Prerequisites +------------- + +Here are some packages that are worth installing if you are doing sandbox or +tools development in U-Boot: + + python3-pytest lzma lzma-alone lz4 python3 python3-virtualenv + libssl1.0-dev + + Basic Operation --------------- -- cgit v1.1