From d9b94f28a442b0013caef99de084d7b72e2d4607 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 25 Jul 2005 14:05:07 -0500 Subject: * Patch by Jon Loeliger, 2005-05-05 Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O --- doc/README.mpc85xxads | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'doc/README.mpc85xxads') diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index c488f2a..08d6831 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -143,6 +143,7 @@ Updated 13-July-2004 Jon Loeliger CONFIG_DDR_ECC only for ECC DDR module CONFIG_DDR_DLL DLL fix on some ADS boards needed for more stability. + CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. Other than the above definitions, the rest in the config files are straightforward. @@ -190,10 +191,10 @@ straightforward. 4.4 Reflash U-boot Image using U-boot - => tftp 10000 u-boot.bin - => protect off fff80000 ffffffff - => erase fff80000 ffffffff - => cp.b 10000 fff80000 80000 + tftp 10000 u-boot.bin + protect off fff80000 ffffffff + erase fff80000 ffffffff + cp.b 10000 fff80000 80000 4.5 Reflash U-Boot with a BDI-2000 -- cgit v1.1