From ed54e6212518262d27abe5e6de3c608d5ebceafb Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Wed, 24 Nov 2004 23:35:19 +0000
Subject: * Fix udelay() on AT91RM9200 for delays < 1 ms.

* Enable long help on CMC PU2 board;
  fix reset issue;
  increase CPU speed from 179 to 207 MHz.
---
 cpu/at91rm9200/cpu.c | 14 ++++++++++++++
 cpu/pxa/interrupts.c | 11 ++++++++---
 2 files changed, 22 insertions(+), 3 deletions(-)

(limited to 'cpu')

diff --git a/cpu/at91rm9200/cpu.c b/cpu/at91rm9200/cpu.c
index a464f29..71463c9 100644
--- a/cpu/at91rm9200/cpu.c
+++ b/cpu/at91rm9200/cpu.c
@@ -134,12 +134,26 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
    /*shutdown the console to avoid strange chars during reset */
    us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
 
+#ifdef CONFIG_AT91RM9200DK 
    /* Clear PA19 to trigger the hard reset */
    pio->PIO_CODR = 0x00080000;
    pio->PIO_OER  = 0x00080000;
    pio->PIO_PER  = 0x00080000;
+#endif
+#ifdef CONFIG_CMC_PU2
+/* this is the way Linux does it */
+#define AT91C_ST_RSTEN (0x1 << 16)
+#define AT91C_ST_EXTEN (0x1 << 17)
+#define AT91C_ST_WDRST (0x1 <<  0)
+/* watchdog mode register */
+#define ST_WDMR *((unsigned long *)0xfffffd08)
+/* system clock control register */
+#define ST_CR *((unsigned long *)0xfffffd00)
+	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+	ST_CR = AT91C_ST_WDRST;
    /* Never reached */
 #endif
+#endif
    return 0;
 }
 
diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c
index 8aec0b9..fd02154 100644
--- a/cpu/pxa/interrupts.c
+++ b/cpu/pxa/interrupts.c
@@ -193,9 +193,14 @@ void udelay_masked (unsigned long usec)
 {
 	ulong tmo;
 
-	tmo = usec / 1000;
-	tmo *= CFG_HZ;
-	tmo /= 1000;
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CFG_HZ;
+		tmo /= 1000;
+	} else {
+		tmo = usec * CFG_HZ;
+		tmo /= (1000*1000);
+	}
 
 	reset_timer_masked ();
 
-- 
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