From 569a191a864cee66e3d0763179e8688499de0377 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2015 18:09:52 +0100 Subject: arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See --- V2: Update the defconfig as per Tom's request --- configs/socfpga_vining_fpga_defconfig | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 configs/socfpga_vining_fpga_defconfig (limited to 'configs') diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig new file mode 100644 index 0000000..f8bb9a6 --- /dev/null +++ b/configs/socfpga_vining_fpga_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DM=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_FIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="samtec" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 -- cgit v1.1 From 5bb4050df36f016de106c0ab129319795acabc06 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 May 2016 17:09:48 +0200 Subject: arm: socfpga: Enable tiny printf and simple malloc in SPL Enable both features to reduce the SPL size by 6 kiB. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Pavel Machek Cc: Stefan Roese --- configs/socfpga_arria5_defconfig | 2 ++ configs/socfpga_cyclone5_defconfig | 2 ++ configs/socfpga_de0_nano_soc_defconfig | 2 ++ configs/socfpga_mcvevk_defconfig | 2 ++ configs/socfpga_sockit_defconfig | 2 ++ configs/socfpga_socrates_defconfig | 2 ++ configs/socfpga_sr1500_defconfig | 2 ++ configs/socfpga_vining_fpga_defconfig | 2 ++ 8 files changed, 16 insertions(+) (limited to 'configs') diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a662e72..ec40ec7 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index b2933f7..8e5c527 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index f197b6d..034a215 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 6624f9e..133a6eb 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index c6414f8..8b1bcfc 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index b47a560..56284a1 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index aab4498..d66f7c6 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_SR1500=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index f8bb9a6..6ce4def 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y -- cgit v1.1