From 5ce94c74a6b59922d4280573f2438e4f5f9b29a8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 18 Oct 2019 15:54:14 +0800 Subject: rockchip: rk3399: defconfig: no need to reserve IRAM for SPL We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang --- configs/nanopc-t4-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'configs/nanopc-t4-rk3399_defconfig') diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 1d4c8f8..b266b3f 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 -- cgit v1.1