From ec48b6c991f400c8583ac2f875d65a8539f0b437 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 22 Aug 2018 14:55:27 +0200 Subject: arm64: versal: Add support for new Xilinx Versal ACAPs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek --- board/xilinx/versal/MAINTAINERS | 7 ++++ board/xilinx/versal/Makefile | 7 ++++ board/xilinx/versal/board.c | 81 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 board/xilinx/versal/MAINTAINERS create mode 100644 board/xilinx/versal/Makefile create mode 100644 board/xilinx/versal/board.c (limited to 'board') diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS new file mode 100644 index 0000000..2d2b808 --- /dev/null +++ b/board/xilinx/versal/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX_VERSAL BOARDS +M: Michal Simek +S: Maintained +F: arch/arm/dts/versal* +F: board/xilinx/versal/ +F: include/configs/xilinx_versal* +F: configs/xilinx_versal* diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile new file mode 100644 index 0000000..2b81276 --- /dev/null +++ b/board/xilinx/versal/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 - 2018 Xilinx, Inc. +# Michal Simek +# + +obj-y := board.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c new file mode 100644 index 0000000..2b3a40b --- /dev/null +++ b/board/xilinx/versal/board.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2018 Xilinx, Inc. + * Michal Simek + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + printf("EL Level:\tEL%d\n", current_el()); + + return 0; +} + +int board_early_init_r(void) +{ + if (current_el() == 3) { + u32 val; + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); + } + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + return 0; +} + +void reset_cpu(ulong addr) +{ +} -- cgit v1.1