From 7a9d109b00a207b481b05d8e147673da33ad1cd3 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 9 Nov 2013 10:22:08 +0000 Subject: qemu-malta: rename to just "malta" This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton --- board/imgtec/malta/Makefile | 9 +++++ board/imgtec/malta/lowlevel_init.S | 69 ++++++++++++++++++++++++++++++++++++++ board/imgtec/malta/malta.c | 47 ++++++++++++++++++++++++++ board/qemu-malta/Makefile | 9 ----- board/qemu-malta/lowlevel_init.S | 69 -------------------------------------- board/qemu-malta/qemu-malta.c | 47 -------------------------- 6 files changed, 125 insertions(+), 125 deletions(-) create mode 100644 board/imgtec/malta/Makefile create mode 100644 board/imgtec/malta/lowlevel_init.S create mode 100644 board/imgtec/malta/malta.c delete mode 100644 board/qemu-malta/Makefile delete mode 100644 board/qemu-malta/lowlevel_init.S delete mode 100644 board/qemu-malta/qemu-malta.c (limited to 'board') diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile new file mode 100644 index 0000000..091830d --- /dev/null +++ b/board/imgtec/malta/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = malta.o +obj-y += lowlevel_init.o diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S new file mode 100644 index 0000000..fa0b6a7 --- /dev/null +++ b/board/imgtec/malta/lowlevel_init.S @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include +#include +#include + +#ifdef CONFIG_SYS_BIG_ENDIAN +#define CPU_TO_GT32(_x) ((_x)) +#else +#define CPU_TO_GT32(_x) ( \ + (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ + (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) +#endif + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + + /* + * Load BAR registers of GT64120 as done by YAMON + * + * based on a patch sent by Antony Pavlov + * to the barebox mailing list. + * The subject of the original patch: + * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' + * URL: + * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html + * + * based on write_bootloader() in qemu.git/hw/mips_malta.c + * see GT64120 manual and qemu.git/hw/gt64xxx.c for details + */ + + /* move GT64120 registers from 0x14000000 to 0x1be00000 */ + li t1, KSEG1ADDR(GT_DEF_BASE) + li t0, CPU_TO_GT32(0xdf000000) + sw t0, GT_ISD_OFS(t1) + + /* setup MEM-to-PCI0 mapping */ + li t1, KSEG1ADDR(MALTA_GT_BASE) + + /* setup PCI0 io window to 0x18000000-0x181fffff */ + li t0, CPU_TO_GT32(0xc0000000) + sw t0, GT_PCI0IOLD_OFS(t1) + li t0, CPU_TO_GT32(0x40000000) + sw t0, GT_PCI0IOHD_OFS(t1) + + /* setup PCI0 mem windows */ + li t0, CPU_TO_GT32(0x80000000) + sw t0, GT_PCI0M0LD_OFS(t1) + li t0, CPU_TO_GT32(0x3f000000) + sw t0, GT_PCI0M0HD_OFS(t1) + + li t0, CPU_TO_GT32(0xc1000000) + sw t0, GT_PCI0M1LD_OFS(t1) + li t0, CPU_TO_GT32(0x5e000000) + sw t0, GT_PCI0M1HD_OFS(t1) + + jr ra + nop diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c new file mode 100644 index 0000000..7eddf1c --- /dev/null +++ b/board/imgtec/malta/malta.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include +#include +#include +#include + +phys_size_t initdram(int board_type) +{ + return CONFIG_SYS_MEM_SIZE; +} + +int checkboard(void) +{ + puts("Board: MIPS Malta CoreLV (Qemu)\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +void _machine_restart(void) +{ + void __iomem *reset_base; + + reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); + __raw_writel(GORESET, reset_base); +} + +void pci_init_board(void) +{ + set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); + + gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), + 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, + 0x10000000, 0x10000000, 128 * 1024 * 1024, + 0x00000000, 0x00000000, 0x20000); +} diff --git a/board/qemu-malta/Makefile b/board/qemu-malta/Makefile deleted file mode 100644 index 5d727f6..0000000 --- a/board/qemu-malta/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = qemu-malta.o -obj-y += lowlevel_init.o diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S deleted file mode 100644 index fa0b6a7..0000000 --- a/board/qemu-malta/lowlevel_init.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include - -#include -#include -#include - -#ifdef CONFIG_SYS_BIG_ENDIAN -#define CPU_TO_GT32(_x) ((_x)) -#else -#define CPU_TO_GT32(_x) ( \ - (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ - (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) -#endif - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - - /* - * Load BAR registers of GT64120 as done by YAMON - * - * based on a patch sent by Antony Pavlov - * to the barebox mailing list. - * The subject of the original patch: - * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' - * URL: - * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html - * - * based on write_bootloader() in qemu.git/hw/mips_malta.c - * see GT64120 manual and qemu.git/hw/gt64xxx.c for details - */ - - /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - li t1, KSEG1ADDR(GT_DEF_BASE) - li t0, CPU_TO_GT32(0xdf000000) - sw t0, GT_ISD_OFS(t1) - - /* setup MEM-to-PCI0 mapping */ - li t1, KSEG1ADDR(MALTA_GT_BASE) - - /* setup PCI0 io window to 0x18000000-0x181fffff */ - li t0, CPU_TO_GT32(0xc0000000) - sw t0, GT_PCI0IOLD_OFS(t1) - li t0, CPU_TO_GT32(0x40000000) - sw t0, GT_PCI0IOHD_OFS(t1) - - /* setup PCI0 mem windows */ - li t0, CPU_TO_GT32(0x80000000) - sw t0, GT_PCI0M0LD_OFS(t1) - li t0, CPU_TO_GT32(0x3f000000) - sw t0, GT_PCI0M0HD_OFS(t1) - - li t0, CPU_TO_GT32(0xc1000000) - sw t0, GT_PCI0M1LD_OFS(t1) - li t0, CPU_TO_GT32(0x5e000000) - sw t0, GT_PCI0M1HD_OFS(t1) - - jr ra - nop diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c deleted file mode 100644 index 7eddf1c..0000000 --- a/board/qemu-malta/qemu-malta.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include - -#include -#include -#include -#include - -phys_size_t initdram(int board_type) -{ - return CONFIG_SYS_MEM_SIZE; -} - -int checkboard(void) -{ - puts("Board: MIPS Malta CoreLV (Qemu)\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -void _machine_restart(void) -{ - void __iomem *reset_base; - - reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); - __raw_writel(GORESET, reset_base); -} - -void pci_init_board(void) -{ - set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); - - gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), - 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, - 0x10000000, 0x10000000, 128 * 1024 * 1024, - 0x00000000, 0x00000000, 0x20000); -} -- cgit v1.1