From 6787c1ece07f771629ea5b463a362f9b4c40d2c0 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 14 Dec 2018 16:16:49 +0100 Subject: MSCC: add board support for the Ocelots based evaluation boards Adding the support for 2 boards sharing common code for Ocelot chip: PCB120 and PCB123 Signed-off-by: Gregory CLEMENT --- board/mscc/ocelot/Kconfig | 14 +++++++++++ board/mscc/ocelot/Makefile | 4 ++++ board/mscc/ocelot/ocelot.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 board/mscc/ocelot/Kconfig create mode 100644 board/mscc/ocelot/Makefile create mode 100644 board/mscc/ocelot/ocelot.c (limited to 'board') diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig new file mode 100644 index 0000000..9ddc088 --- /dev/null +++ b/board/mscc/ocelot/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +config SYS_VENDOR + default "mscc" + +if SOC_OCELOT + +config SYS_BOARD + default "ocelot" + +config SYS_CONFIG_NAME + default "ocelot" + +endif diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile new file mode 100644 index 0000000..9f28c81 --- /dev/null +++ b/board/mscc/ocelot/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +obj-$(CONFIG_SOC_OCELOT) := ocelot.o + diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c new file mode 100644 index 0000000..d521a61 --- /dev/null +++ b/board/mscc/ocelot/ocelot.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MSCC_GPIO_ALT0 0x54 +#define MSCC_GPIO_ALT1 0x58 + +void external_cs_manage(struct udevice *dev, bool enable) +{ + u32 cs = spi_chip_select(dev); + /* IF_SI0_OWNER, select the owner of the SI interface + * Encoding: 0: SI Slave + * 1: SI Boot Master + * 2: SI Master Controller + */ + if (!enable) { + writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE | + ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE); + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, + ICPU_GENERAL_CTRL_IF_SI_OWNER_M, + ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); + } else { + writel(0, BASE_CFG + ICPU_SW_MODE); + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, + ICPU_GENERAL_CTRL_IF_SI_OWNER_M, + ICPU_GENERAL_CTRL_IF_SI_OWNER(1)); + } +} + +void board_debug_uart_init(void) +{ + /* too early for the pinctrl driver, so configure the UART pins here */ + setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7)); + clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7)); +} + +int board_early_init_r(void) +{ + /* Prepare SPI controller to be used in master mode */ + writel(0, BASE_CFG + ICPU_SW_MODE); + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, + ICPU_GENERAL_CTRL_IF_SI_OWNER_M, + ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + return 0; +} -- cgit v1.1