From edf0093732225c2fd0791c3864e9a3eef1f92f19 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 29 Aug 2016 20:37:15 -0300 Subject: mx6: ddr: Allow changing REFSEL and REFR fields Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam Reviewed-by: Eric Nelson --- board/wandboard/spl.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board/wandboard') diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 77afae7..085095c 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -187,6 +187,8 @@ static struct mx6_ddr_sysinfo mem_q = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { @@ -228,6 +230,8 @@ static struct mx6_ddr_sysinfo mem_dl = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; /* DDR 32bit 512MB */ @@ -245,6 +249,8 @@ static struct mx6_ddr_sysinfo mem_s = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static void ccgr_init(void) -- cgit v1.1