From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/siemens/CCM/ccm.c | 80 +++++++++++++-------------- board/siemens/CCM/flash.c | 38 ++++++------- board/siemens/CCM/fpga_ccm.c | 4 +- board/siemens/IAD210/IAD210.c | 26 ++++----- board/siemens/IAD210/atm.c | 24 ++++----- board/siemens/IAD210/atm.h | 4 +- board/siemens/IAD210/flash.c | 18 +++---- board/siemens/SCM/config.mk | 2 +- board/siemens/SCM/flash.c | 16 +++--- board/siemens/SCM/fpga_scm.c | 14 ++--- board/siemens/SCM/scm.c | 74 ++++++++++++------------- board/siemens/SMN42/flash.c | 82 ++++++++++++++-------------- board/siemens/pcu_e/flash.c | 26 ++++----- board/siemens/pcu_e/pcu_e.c | 122 +++++++++++++++++++++--------------------- 14 files changed, 265 insertions(+), 265 deletions(-) (limited to 'board/siemens') diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c index d653763..8053da4 100644 --- a/board/siemens/CCM/ccm.c +++ b/board/siemens/CCM/ccm.c @@ -133,7 +133,7 @@ int checkboard (void) int power_on_reset(void) { /* Test Reset Status Register */ - return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; + return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; } #define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ @@ -142,7 +142,7 @@ int power_on_reset(void) static void init_leds (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_cpm.cp_pbpar &= ~PB_LEDS; immap->im_cpm.cp_pbodr &= ~PB_LEDS; @@ -157,7 +157,7 @@ static void init_leds (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size = 0; @@ -171,7 +171,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -180,10 +180,10 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay(200); @@ -203,21 +203,21 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size = size9; /* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay(500); /* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ } @@ -230,7 +230,7 @@ phys_size_t initdram (int board_type) */ if (size < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay(1000); } @@ -238,13 +238,13 @@ phys_size_t initdram (int board_type) * Final mapping */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; can_driver_enable (); @@ -263,7 +263,7 @@ phys_size_t initdram (int board_type) */ void can_driver_enable (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* Initialize MBMR */ @@ -302,13 +302,13 @@ void can_driver_enable (void) memctl->memc_mcr = 0x011C | UPMB; /* Initialize OR3 / BR3 for CAN Bus Controller */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; } void can_driver_disable (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* Reset OR3 / BR3 to disable CAN Bus Controller */ @@ -331,7 +331,7 @@ void can_driver_disable (void) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -341,24 +341,24 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize /* ------------------------------------------------------------------------- */ -#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN) +#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN) void reset_phy(void) { - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; ulong value; /* Configure all needed port pins for GPIO */ -#ifdef CFG_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +#ifdef CONFIG_SYS_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; #else - immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* Set low */ + immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */ #endif - immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET; /* output */ + immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */ + immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */ immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ @@ -366,23 +366,23 @@ void reset_phy(void) value = immr->im_cpm.cp_pbdat; /* Assert Powerdown and Reset signals */ - value |= CFG_PB_ETH_POWERDOWN; + value |= CONFIG_SYS_PB_ETH_POWERDOWN; /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#ifdef CFG_ETH_CFG1_VALUE - value |= CFG_PB_ETH_CFG1; +#ifdef CONFIG_SYS_ETH_CFG1_VALUE + value |= CONFIG_SYS_PB_ETH_CFG1; #else - value &= ~(CFG_PB_ETH_CFG1); + value &= ~(CONFIG_SYS_PB_ETH_CFG1); #endif -#ifdef CFG_ETH_CFG2_VALUE - value |= CFG_PB_ETH_CFG2; +#ifdef CONFIG_SYS_ETH_CFG2_VALUE + value |= CONFIG_SYS_PB_ETH_CFG2; #else - value &= ~(CFG_PB_ETH_CFG2); + value &= ~(CONFIG_SYS_PB_ETH_CFG2); #endif -#ifdef CFG_ETH_CFG3_VALUE - value |= CFG_PB_ETH_CFG3; +#ifdef CONFIG_SYS_ETH_CFG3_VALUE + value |= CONFIG_SYS_PB_ETH_CFG3; #else - value &= ~(CFG_PB_ETH_CFG3); + value &= ~(CONFIG_SYS_PB_ETH_CFG3); #endif /* Drive output signals to initial state */ @@ -391,11 +391,11 @@ void reset_phy(void) udelay (10000); /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ udelay (10000); /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET; + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET; udelay (1000); } diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c index 9c32785..ad1ed79 100644 --- a/board/siemens/CCM/flash.c +++ b/board/siemens/CCM/flash.c @@ -24,7 +24,7 @@ #include #include -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif } else { @@ -419,7 +419,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -542,7 +542,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c index 11b97bc..50b08ab 100644 --- a/board/siemens/CCM/fpga_ccm.c +++ b/board/siemens/CCM/fpga_ccm.c @@ -31,7 +31,7 @@ fpga_t fpga_list[] = { { "PUMA" , PUMA_CONF_BASE , - CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE } + CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE } }; int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); @@ -90,7 +90,7 @@ const uint puma_table[] = ulong fpga_control (fpga_t* fpga, int cmd) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; switch (cmd) { diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c index 9c0ff02..e9e7f84 100644 --- a/board/siemens/IAD210/IAD210.c +++ b/board/siemens/IAD210/IAD210.c @@ -102,7 +102,7 @@ const uint sdram_table[] = { phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile iop8xx_t *iop = &immap->im_ioport; volatile fec_t *fecp = &immap->im_cpm.cp_fec; @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000088; @@ -126,10 +126,10 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -155,20 +155,20 @@ phys_size_t initdram (int board_type) * Check Bank 0 Memory Size for re-configuration * */ - size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM, + size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); udelay (1000); - memctl->memc_mamr = CFG_MAMR; + memctl->memc_mamr = CONFIG_SYS_MAMR; udelay (1000); /* * Final mapping */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); udelay (10000); @@ -195,7 +195,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -219,7 +219,7 @@ void board_serial_init (void) void board_ether_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *iop = &immap->im_ioport; volatile fec_t *fecp = &immap->im_cpm.cp_fec; @@ -230,7 +230,7 @@ void board_ether_init (void) int board_early_init_f (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile iop8xx_t *iop = &immap->im_ioport; @@ -261,7 +261,7 @@ int board_early_init_f (void) void board_get_enetaddr (uchar * addr) { int i; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cpm = &immap->im_cpm; unsigned int rccrtmp; diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c index 1b27f33..d1b75bc 100644 --- a/board/siemens/IAD210/atm.c +++ b/board/siemens/IAD210/atm.c @@ -57,7 +57,7 @@ void atmUtpInit(void); ****************************************************************************/ int atmLoad() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; volatile iop8xx_t *iop = &immap->im_ioport; @@ -91,7 +91,7 @@ int atmLoad() ****************************************************************************/ void atmUnload() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; volatile iop8xx_t *iop = &immap->im_ioport; @@ -141,11 +141,11 @@ void atmUnload() int atmMemInit() { int i; - unsigned immr = CFG_IMMR; + unsigned immr = CONFIG_SYS_IMMR; int total_num_rbd = 0; int total_num_tbd = 0; - memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); + memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY; @@ -226,11 +226,11 @@ void atmIntInit() void atmApcInit() { int i; - /* unsigned immr = CFG_IMMR; */ - uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR); - struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR); - uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR); - uint16 * tq_ptr = TQ_PTR(CFG_IMMR); + /* unsigned immr = CONFIG_SYS_IMMR; */ + uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR); + struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR); + uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR); + uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR); /***************************************************/ /* Initialize MPHY Pointing Table (only one entry) */ /***************************************************/ @@ -290,7 +290,7 @@ void atmApcInit() ****************************************************************************/ void atmAmtInit() { - unsigned immr = CFG_IMMR; + unsigned immr = CONFIG_SYS_IMMR; g_atm.am_top = AM_PTR(immr); g_atm.ap_top = AP_PTR(immr); @@ -315,7 +315,7 @@ void atmAmtInit() ****************************************************************************/ void atmCpmInit() { - unsigned immr = CFG_IMMR; + unsigned immr = CONFIG_SYS_IMMR; memset((char *)immr + 0x3F00, 0x00, 0xC0); @@ -551,7 +551,7 @@ void atmCpmInit() ****************************************************************************/ void atmUtpInit() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile iop8xx_t *iop = &immap->im_ioport; volatile car8xx_t *car = &immap->im_clkrst; volatile cpm8xx_t *cpm = &immap->im_cpm; diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h index 71b0497..cd5b45e 100644 --- a/board/siemens/IAD210/atm.h +++ b/board/siemens/IAD210/atm.h @@ -6,9 +6,9 @@ typedef volatile unsigned short vuint16; typedef volatile unsigned int vuint32; -#define DPRAM_ATM CFG_IMMR + 0x3000 +#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000 -#define ATM_DPRAM_BEGIN (DPRAM_ATM - CFG_IMMR - 0x2000) +#define ATM_DPRAM_BEGIN (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000) #define NUM_CONNECTIONS 1 #define SAR_RXB_SIZE 1584 #define AM_HMASK 0x0FFFFFF0 diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c index 110858d..c262e0f 100644 --- a/board/siemens/IAD210/flash.c +++ b/board/siemens/IAD210/flash.c @@ -24,7 +24,7 @@ #include #include -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; int i; /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size; @@ -368,7 +368,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -491,7 +491,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/siemens/SCM/config.mk b/board/siemens/SCM/config.mk index 855ae38..5d0898b 100644 --- a/board/siemens/SCM/config.mk +++ b/board/siemens/SCM/config.mk @@ -25,7 +25,7 @@ # Siemens SCM boards # -# This should be equal to the CFG_FLASH_BASE define in config_SCM.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_SCM.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c index 500af92..4a6d538 100644 --- a/board/siemens/SCM/flash.c +++ b/board/siemens/SCM/flash.c @@ -31,7 +31,7 @@ #define V_BYTE(a) (*(volatile unsigned char *)( a )) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- @@ -185,13 +185,13 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 >> 20); @@ -201,10 +201,10 @@ unsigned long flash_init (void) * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) @@ -364,7 +364,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -480,7 +480,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) start = get_timer (0); while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c index 661bf66..acd9c15 100644 --- a/board/siemens/SCM/fpga_scm.c +++ b/board/siemens/SCM/fpga_scm.c @@ -28,18 +28,18 @@ #include "../common/fpga.h" fpga_t fpga_list[] = { - {"FIOX", CFG_FIOX_BASE, - CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE} + {"FIOX", CONFIG_SYS_FIOX_BASE, + CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE} , - {"FDOHM", CFG_FDOHM_BASE, - CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE} + {"FDOHM", CONFIG_SYS_FDOHM_BASE, + CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE} }; int fpga_count = sizeof (fpga_list) / sizeof (fpga_t); ulong fpga_control (fpga_t * fpga, int cmd) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; switch (cmd) { case FPGA_INIT_IS_HIGH: @@ -74,11 +74,11 @@ ulong fpga_control (fpga_t * fpga, int cmd) break; case FPGA_GET_ID: - if (fpga->conf_base == CFG_FIOX_BASE) { + if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) { ulong ver = *(volatile ulong *) (fpga->conf_base + 0x10); return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0); - } else if (fpga->conf_base == CFG_FDOHM_BASE) { + } else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) { return (*(volatile ushort *) fpga->conf_base) & 0xff; } else { return *(volatile ulong *) fpga->conf_base; diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index 6a9dd25..e0611fe 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -249,7 +249,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; @@ -274,7 +274,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -285,7 +285,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -308,10 +308,10 @@ int power_on_reset (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif long psize, lsize; @@ -319,8 +319,8 @@ phys_size_t initdram (int board_type) psize = 16 * 1024 * 1024; lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; #if 0 /* Just for debugging */ #define prt_br_or(brX,orX) do { \ @@ -338,37 +338,37 @@ phys_size_t initdram (int board_type) prt_br_or (br3, or3); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL - %ld MB, ", psize >> 20); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL - %ld MB, ", psize >> 20); } /* Local SDRAM setup: */ -#ifdef CFG_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CFG_LSRT; - size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, +#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CONFIG_SYS_LSRT; + size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, (uchar *) SDRAM_BASE2_PRELIM); if (size8 < size9) { lsize = size9; printf ("Local:9COL - %ld MB) using ", lsize >> 20); } else { - lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); printf ("Local:8COL - %ld MB) using ", lsize >> 20); } @@ -377,11 +377,11 @@ phys_size_t initdram (int board_type) /* Set up BR2 so that the local SDRAM goes * right after the 60x SDRAM */ - memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | - (CFG_SDRAM_BASE + psize); + memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | + (CONFIG_SYS_SDRAM_BASE + psize); #endif -#endif /* CFG_INIT_LOCAL_SDRAM */ -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -394,17 +394,17 @@ phys_size_t initdram (int board_type) static void config_scoh_cs (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; - volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE; + volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE; volatile uint tmp, i; /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ - memctl->memc_or3 = CFG_CAN0_OR3; - memctl->memc_br3 = CFG_CAN0_BR3; + memctl->memc_or3 = CONFIG_SYS_CAN0_OR3; + memctl->memc_br3 = CONFIG_SYS_CAN0_BR3; /* Initialize OR4 / BR4 for CAN Bus Controller 1 */ - memctl->memc_or4 = CFG_CAN1_OR4; - memctl->memc_br4 = CFG_CAN1_BR4; + memctl->memc_or4 = CONFIG_SYS_CAN1_OR4; + memctl->memc_br4 = CONFIG_SYS_CAN1_BR4; /* Initialize MAMR to write in the array at address 0x0 */ memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS; @@ -487,19 +487,19 @@ static void config_scoh_cs (void) /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */ - memctl->memc_or5 = CFG_EXTPROM_OR5; - memctl->memc_br5 = CFG_EXTPROM_BR5; + memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5; + memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5; /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */ - memctl->memc_or6 = CFG_EXTPROM_OR6; - memctl->memc_br6 = CFG_EXTPROM_BR6; + memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6; + memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6; /* Initialize OR7 / BR7 for the Glue Logic */ - memctl->memc_or7 = CFG_FIOX_OR7; - memctl->memc_br7 = CFG_FIOX_BR7; + memctl->memc_or7 = CONFIG_SYS_FIOX_OR7; + memctl->memc_br7 = CONFIG_SYS_FIOX_BR7; /* Initialize OR8 / BR8 for the DOH Logic */ - memctl->memc_or8 = CFG_FDOHM_OR8; - memctl->memc_br8 = CFG_FDOHM_BR8; + memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8; + memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8; DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0); DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1); diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c index ae64096..8cf17b8 100644 --- a/board/siemens/SMN42/flash.c +++ b/board/siemens/SMN42/flash.c @@ -25,8 +25,8 @@ #include #include -static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +static unsigned long flash_addr_table[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS_LIST; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong); extern int lpc2292_flash_erase(flash_info_t *, int, int); @@ -172,19 +172,19 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * From here on is code for the external S29GL128N taken from cam5200_flash.c */ -#define CFG_FLASH_WORD_SIZE unsigned short +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short static int wait_for_DQ7_32(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -199,8 +199,8 @@ static int wait_for_DQ7_32(flash_info_t * info, int sect) int ext_flash_erase(flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect, ret; ret = 0; @@ -236,14 +236,14 @@ int ext_flash_erase(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ l_sect = sect; /* @@ -269,8 +269,8 @@ int ext_flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ if (ret) printf(" error\n"); @@ -282,20 +282,20 @@ int ext_flash_erase(flash_info_t * info, int s_first, int s_last) static ulong flash_get_size(vu_long * addr, flash_info_t * info) { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; default: @@ -308,12 +308,12 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) value = addr2[1]; /* device ID */ switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_MIRROR: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_MIRROR: value = addr2[14]; switch(value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_2: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_2: value = addr2[15]; - if (value != (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_3) { + if (value != (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_3) { info->flash_id = FLASH_UNKNOWN; } else { info->flash_id += FLASH_S29GL128N; @@ -340,13 +340,13 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); info->protect[i] = addr2[2] & 1; } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -354,11 +354,11 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) static unsigned long ext_flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; int i; /* Init: no FLASHes known */ - for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -384,9 +384,9 @@ static unsigned long ext_flash_init(void) static int write_word(flash_info_t * info, ulong dest, ushort data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) &data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) &data; ulong start; int flag; @@ -398,9 +398,9 @@ static int write_word(flash_info_t * info, ulong dest, ushort data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; *dest2 = *data2; /* re-enable interrupts if necessary */ @@ -409,10 +409,10 @@ static int write_word(flash_info_t * info, ulong dest, ushort data) /* data polling for D7 */ start = get_timer(0); - while ((*dest2 & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (*data2 & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((*dest2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (*data2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf("WRITE_TOUT\n"); return (1); } diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c index 97b511e..3ce7bb3 100644 --- a/board/siemens/pcu_e/flash.c +++ b/board/siemens/pcu_e/flash.c @@ -26,7 +26,7 @@ #if defined(CONFIG_ENV_IS_IN_FLASH) # ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET) +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif # ifndef CONFIG_ENV_SIZE # define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE @@ -47,7 +47,7 @@ /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -68,20 +68,20 @@ static void flash_get_offsets (ulong base, flash_info_t *info); */ #define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \ - - (0xFFFFFFFF - CFG_MONITOR_BASE) ) + - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) ) /*----------------------------------------------------------------------- */ unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long base, size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", @@ -162,7 +162,7 @@ unsigned long flash_init (void) if (size_b1) { flash_info_t tmp_info; - memctl->memc_or6 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; @@ -437,10 +437,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) #endif } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } saddr = (vu_short *)info->start[0]; @@ -526,7 +526,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_short*)(info->start[l_sect]); while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -660,7 +660,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); - for (passed=0; passed < CFG_FLASH_WRITE_TOUT; passed=get_timer(start)) { + for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) { sval = *sdest; @@ -683,7 +683,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data) dest, sval, sdata); } - if (passed >= CFG_FLASH_WRITE_TOUT) { + if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) { DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n", dest, sval, sdata); rc = 1; diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c index 5647f7a..a60c825 100644 --- a/board/siemens/pcu_e/pcu_e.c +++ b/board/siemens/pcu_e/pcu_e.c @@ -158,7 +158,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; long int size_b0, reg; int i; @@ -169,7 +169,7 @@ phys_size_t initdram (int board_type) upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* burst length=4, burst type=sequential, CAS latency=2 */ memctl->memc_mar = 0x00000088; @@ -178,15 +178,15 @@ phys_size_t initdram (int board_type) * Map controller bank 2 to the SDRAM bank at preliminary address. */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; + memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; + memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #else /* XXX */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif /* XXX */ /* initialize memory address register */ - memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */ /* mode initialization (offset 5) */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ @@ -241,12 +241,12 @@ phys_size_t initdram (int board_type) * Check Bank 0 Memory Size for re-configuration */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ - size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); + size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); #else /* XXX */ - size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); #endif /* XXX */ - memctl->memc_mamr = CFG_MAMR | MAMR_PTAE; + memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE; /* * Final mapping: @@ -254,10 +254,10 @@ phys_size_t initdram (int board_type) #if PCU_E_WITH_SWAPPED_CS /* XXX */ memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; #else /* XXX */ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; #endif /* XXX */ udelay (1000); @@ -283,7 +283,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; memctl->memc_mamr = mamr_value; @@ -294,29 +294,29 @@ static long int dram_size (long int mamr_value, long int *base, /* ------------------------------------------------------------------------- */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) #else /* XXX */ -#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \ - CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \ + CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) #endif /* XXX */ -#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET) +#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET) void reset_phy (void) { - immap_t *immr = (immap_t *) CFG_IMMR; + immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ulong value; /* Configure all needed port pins for GPIO */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ -# ifdef CFG_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +# ifdef CONFIG_SYS_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; # else - immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */ + immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */ # endif - immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */ + immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */ + immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */ #endif /* XXX */ immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ @@ -324,31 +324,31 @@ void reset_phy (void) value = immr->im_cpm.cp_pbdat; /* Assert Powerdown and Reset signals */ - value |= CFG_PB_ETH_POWERDOWN; - value &= ~(CFG_PB_ETH_RESET); + value |= CONFIG_SYS_PB_ETH_POWERDOWN; + value &= ~(CONFIG_SYS_PB_ETH_RESET); /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ #if !PCU_E_WITH_SWAPPED_CS -# ifdef CFG_ETH_MDDIS_VALUE - value |= CFG_PB_ETH_MDDIS; +# ifdef CONFIG_SYS_ETH_MDDIS_VALUE + value |= CONFIG_SYS_PB_ETH_MDDIS; # else - value &= ~(CFG_PB_ETH_MDDIS); + value &= ~(CONFIG_SYS_PB_ETH_MDDIS); # endif #endif -#ifdef CFG_ETH_CFG1_VALUE - value |= CFG_PB_ETH_CFG1; +#ifdef CONFIG_SYS_ETH_CFG1_VALUE + value |= CONFIG_SYS_PB_ETH_CFG1; #else - value &= ~(CFG_PB_ETH_CFG1); + value &= ~(CONFIG_SYS_PB_ETH_CFG1); #endif -#ifdef CFG_ETH_CFG2_VALUE - value |= CFG_PB_ETH_CFG2; +#ifdef CONFIG_SYS_ETH_CFG2_VALUE + value |= CONFIG_SYS_PB_ETH_CFG2; #else - value &= ~(CFG_PB_ETH_CFG2); + value &= ~(CONFIG_SYS_PB_ETH_CFG2); #endif -#ifdef CFG_ETH_CFG3_VALUE - value |= CFG_PB_ETH_CFG3; +#ifdef CONFIG_SYS_ETH_CFG3_VALUE + value |= CONFIG_SYS_PB_ETH_CFG3; #else - value &= ~(CFG_PB_ETH_CFG3); + value &= ~(CONFIG_SYS_PB_ETH_CFG3); #endif /* Drive output signals to initial state */ @@ -357,11 +357,11 @@ void reset_phy (void) udelay (10000); /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ udelay (10000); /* de-assert RESET signal of PHY */ - immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET; + immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET; udelay (1000); } @@ -414,7 +414,7 @@ U_BOOT_CMD (puma, 4, 1, do_puma, static void puma_set_mode (int mode) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; /* disable PUMA in memory controller */ @@ -452,7 +452,7 @@ static void puma_set_mode (int mode) static void puma_load (ulong addr, ulong len) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */ uchar *data = (uchar *) addr; int i; @@ -462,33 +462,33 @@ static void puma_load (ulong addr, ulong len) ++len; /* Reset FPGA */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */ - immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT); - immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT); + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */ + immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT); + immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT); #if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */ - immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */ + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */ + immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */ #else - immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */ - immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */ + immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */ + immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */ + immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */ + immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */ #endif /* XXX */ udelay (100); #if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */ + immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */ #else - immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */ + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */ #endif /* XXX */ /* wait until INIT indicates completion of reset */ for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) { udelay (1000); - if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT) + if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT) break; } if (i == PUMA_INIT_TIMEOUT) { @@ -519,14 +519,14 @@ static void puma_status (void) static int puma_init_done (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* make sure pin is GPIO input */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE); - immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE); - immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE); + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE); + immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE); + immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE); - return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0; + return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0; } /* ------------------------------------------------------------------------- */ -- cgit v1.1