From e95b61cfb0c7203964c1a3f163e16a65f04d87ec Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Mon, 4 Nov 2002 16:02:40 +0000
Subject: Patch by Guillaume Alexandre,, 04 Nov 2002: Improve PCI access on
 32-bits Compact PCI bus

Adjust VFD initialization on TRAB

Cleanup RRvision video code
---
 board/pcippc2/pcippc2.c      | 21 +++++++++++++++++++++
 board/pcippc2/pcippc2.h      |  2 ++
 board/pcippc2/pcippc2_fpga.h |  1 +
 3 files changed, 24 insertions(+)

(limited to 'board/pcippc2')

diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
index e1b065b..80ca402 100644
--- a/board/pcippc2/pcippc2.c
+++ b/board/pcippc2/pcippc2.c
@@ -117,6 +117,8 @@ int misc_init_r (void)
 {
 	pcippc2_fpga_init ();
 
+	pcippc2_cpci3264_init ();
+
 #if defined(CONFIG_WATCHDOG)
 	pcippc2_wdt_init ();
 #endif
@@ -147,6 +149,25 @@ void doc_init (void)
 	doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
 }
 
+void pcippc2_cpci3264_init (void)
+{
+  pci_dev_t		bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
+
+  if (bdf == -1)
+  {
+    puts("Unable to find FPGA !\n");
+    hang();
+  }
+
+	if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
+	/* 32-bits Compact PCI bus - LSB bit */
+	{
+		iobarrier_rw();
+		out32(BRIDGE(CPCI, PCIDG), 0x40000000);	/* 32-bits bridge, Pipeline */
+		iobarrier_rw();
+	}
+}
+
 #if defined(CONFIG_WATCHDOG)
 
 void pcippc2_wdt_init (void)
diff --git a/board/pcippc2/pcippc2.h b/board/pcippc2/pcippc2.h
index 6e9e2ff..3820bbe 100644
--- a/board/pcippc2/pcippc2.h
+++ b/board/pcippc2/pcippc2.h
@@ -40,6 +40,8 @@ extern u32	pcippc2_sdram_size		(void);
 
 extern void 	pcippc2_fpga_init		(void);
 
+extern void 	pcippc2_cpci3264_init	(void);
+
 extern void 	cpc710_pci_init			(void);
 extern void	cpc710_pci_enable_timeout	(void);
 
diff --git a/board/pcippc2/pcippc2_fpga.h b/board/pcippc2/pcippc2_fpga.h
index b6206a4..850c331 100644
--- a/board/pcippc2/pcippc2_fpga.h
+++ b/board/pcippc2/pcippc2_fpga.h
@@ -28,6 +28,7 @@
 #define FPGA_DEVICE_ID			0x000d
 
 #define HW_FPGA0_INT			0x0000
+#define HW_FPGA0_BOARD		0x0060
 #define HW_FPGA0_UART1			0x0080
 #define HW_FPGA0_UART2			0x0100
 #define HW_FPGA0_RTC			0x2000
-- 
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