From f70e00fa7da69d16379c0b3526b793be45cd055d Mon Sep 17 00:00:00 2001 From: Yau Wai Gan Date: Tue, 24 May 2022 15:02:28 +0800 Subject: arm: dts: socfpga: stratix10: Update MMC smplsel value This new MMC sample select value is obtained from running tests on multiple Stratix 10 boards and proven working. Signed-off-by: Yau Wai Gan Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index b7b48a5..8aa55a6 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -92,7 +92,7 @@ broken-cd; bus-width = <4>; drvsel = <3>; - smplsel = <0>; + smplsel = <2>; }; &qspi { -- cgit v1.1 From 373c1428a0374c29f19cca76f12c0e93378a634a Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Wed, 1 Jun 2022 15:54:59 +0800 Subject: arch: arm: socfpga: timer_s10: Override udelay for secure section Override __udelay() as 'always inlined' function so that PSCI code run in '__secure' section can call this delay function as well. Signed-off-by: Chee Hong Ang Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/timer_s10.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 7d5598e..84b13ce 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017-2018 Intel Corporation + * Copyright (C) 2017-2022 Intel Corporation * */ #include #include +#include #include #include @@ -26,3 +27,34 @@ int timer_init(void) #endif return 0; } + +__always_inline u64 __get_time_stamp(void) +{ + u64 cntpct; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + + return cntpct; +} + +__always_inline uint64_t __usec_to_tick(unsigned long usec) +{ + u64 tick = usec; + u64 cntfrq; + + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + tick *= cntfrq; + do_div(tick, 1000000); + + return tick; +} + +__always_inline void __udelay(unsigned long usec) +{ + /* get current timestamp */ + u64 tmp = __get_time_stamp() + __usec_to_tick(usec); + + while (__get_time_stamp() < tmp + 1) /* loop till event */ + ; +} \ No newline at end of file -- cgit v1.1 From 7f8533078291bc1c96125ec0619ffd5d01ecc83d Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Tue, 31 May 2022 16:05:56 +0800 Subject: arm: dts: socfpga: agilex: Add freeze controller node The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 6cac36a..2400fad 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2019-2022 Intel Corporation */ #include "socfpga_agilex-u-boot.dtsi" @@ -11,6 +11,15 @@ aliases { spi0 = &qspi; i2c0 = &i2c1; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; memory { -- cgit v1.1 From 5474fb894cba4de1f8735e02155ca85d81af03de Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Tue, 31 May 2022 16:15:17 +0800 Subject: arm: dts: socfpga: stratix10: Add freeze controller node The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 61df425..75a2904 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation + * Copyright (C) 2019-2022 Intel Corporation */ #include "socfpga_stratix10-u-boot.dtsi" @@ -10,6 +10,15 @@ /{ aliases { spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; }; -- cgit v1.1