From 8eeb19be753da220819b0b3a95a746508455d149 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:55:30 +0000 Subject: mx31: Move EHCI definitions to ehci-fsl.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic --- arch/arm/include/asm/arch-mx31/imx-regs.h | 26 -------------------------- 1 file changed, 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 8fd3d08..01a849d 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -896,32 +896,6 @@ struct esdc_regs { #define MX31_AIPS1_BASE_ADDR 0x43f00000 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) -/* USB portsc */ -/* values for portsc field */ -#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) -#define MXC_EHCI_FORCE_FS (1 << 24) -#define MXC_EHCI_UTMI_8BIT (0 << 28) -#define MXC_EHCI_UTMI_16BIT (1 << 28) -#define MXC_EHCI_SERIAL (1 << 29) -#define MXC_EHCI_MODE_UTMI (0 << 30) -#define MXC_EHCI_MODE_PHILIPS (1 << 30) -#define MXC_EHCI_MODE_ULPI (2 << 30) -#define MXC_EHCI_MODE_SERIAL (3 << 30) - -/* values for flags field */ -#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) -#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) -#define MXC_EHCI_INTERFACE_MASK (0xf) - -#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_TTL_ENABLED (1 << 6) - -#define MXC_EHCI_INTERNAL_PHY (1 << 7) -#define MXC_EHCI_IPPUE_DOWN (1 << 8) -#define MXC_EHCI_IPPUE_UP (1 << 9) - /* * CSPI register definitions */ -- cgit v1.1 From 34d33b671a03da1c115d83a603fb36da0360b20a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:57:59 +0000 Subject: ehci-mxc: Define host offsets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic --- arch/arm/include/asm/arch-mx25/imx-regs.h | 1 + arch/arm/include/asm/arch-mx31/imx-regs.h | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 738d411..5f4b543 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -241,6 +241,7 @@ struct aips_regs { #define IMX_RTIC_BASE (0x53FEC000) #define IMX_IIM_BASE (0x53FF0000) #define IMX_USB_BASE (0x53FF4000) +#define IMX_USB_PORT_OFFSET 0x200 #define IMX_CSI_BASE (0x53FF8000) #define IMX_DRYICE_BASE (0x53FFC000) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 01a849d..ae3658b 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -895,6 +895,7 @@ struct esdc_regs { #define MX31_AIPS1_BASE_ADDR 0x43f00000 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) +#define IMX_USB_PORT_OFFSET 0x200 /* * CSPI register definitions -- cgit v1.1 From 71a5c55bfa776b29d11b85e80945b89af06e6546 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:58:12 +0000 Subject: ehci-mxc: Add support for i.MX35 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic --- arch/arm/include/asm/arch-mx35/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 7b6475a..18c6816 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -84,6 +84,8 @@ #define PWM_BASE_ADDR 0x53FE0000 #define RTIC_BASE_ADDR 0x53FEC000 #define IIM_BASE_ADDR 0x53FF0000 +#define IMX_USB_BASE 0x53FF4000 +#define IMX_USB_PORT_OFFSET 0x400 #define IMX_CCM_BASE CCM_BASE_ADDR -- cgit v1.1 From d84f56f48f361df182060f702c20a49c12937504 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 15 Nov 2012 11:23:21 +0000 Subject: mx5: Align SPI CS naming with i.MX53 reference manual Align SPI chip select naming with i.MX53 reference manual. Signed-off-by: Fabio Estevam --- arch/arm/include/asm/arch-mx5/mx5x_pins.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h index 122fbee..3457f6a 100644 --- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h +++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h @@ -802,22 +802,22 @@ typedef enum iomux_input_select { MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, MX53_CSPI_IPP_IND_MISO_SELECT_INPUT, MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT, MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, - MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT, MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT, MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT, MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, - MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT, MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT, MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, - MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT, MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT, MX53_ESAI1_IPP_IND_FST_SELECT_INPUT, MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT, -- cgit v1.1 From 081237c1f7e7a177bb2e761ee5678d08c345865d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 15 Nov 2012 11:23:22 +0000 Subject: mx5: Print CSPI clock in 'clock' command Print CSPI clock in 'clock' command. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/clock.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 1c9223f..76c2c52 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -928,7 +928,9 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); - +#ifdef CONFIG_MXC_SPI + printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); +#endif return 0; } -- cgit v1.1 From cc446726de6032688227548ef9d4b2eff331df83 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 01:30:10 +0000 Subject: mx6: clock: Only show CSPI clock if CSPI is enabled If a board does not enable CSPI, there is no need to show the CSPI clock frequency as part of the 'clock' command. Reported-by: Dirk Behme Signed-off-by: Fabio Estevam Acked-by: Dirk Behme --- arch/arm/cpu/armv7/mx6/clock.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index a01d96f..a50db70 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -404,7 +404,9 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("\n"); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); +#ifdef CONFIG_MXC_SPI printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); +#endif printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); -- cgit v1.1 From 39e8576164c3bef9d6cb9ad4567c09fc6a87b5fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Mon, 5 Nov 2012 10:07:04 +0000 Subject: mx5: Mark lowlevel_init board-specific code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Matt Sealey Acked-by: Stefano Babic --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 29ec957..6d9396a9 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -396,7 +396,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 -- cgit v1.1 From 90a21030e330645d559a488f806c087809305eff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 21 Nov 2012 16:50:39 +0000 Subject: mx28: Fix typo in POWER_MINPWR_VBG_OFF The POWER_MINPWR_VBG_OFF bit in mx28 power supply block is not called POWER_MINPWR_FBG_OFF, but POWER_MINPWR_VBG_OFF. Correct the name in the header file. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/include/asm/arch-mxs/regs-power.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mxs/regs-power.h b/arch/arm/include/asm/arch-mxs/regs-power.h index a46a372..3c98cce 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power.h +++ b/arch/arm/include/asm/arch-mxs/regs-power.h @@ -128,7 +128,7 @@ struct mxs_power_regs { #define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) #define POWER_MINPWR_ENABLE_OSC (1 << 9) #define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_FBG_OFF (1 << 7) +#define POWER_MINPWR_VBG_OFF (1 << 7) #define POWER_MINPWR_DOUBLE_FETS (1 << 6) #define POWER_MINPWR_HALFFETS (1 << 5) #define POWER_MINPWR_LESSANA_I (1 << 4) -- cgit v1.1 From 1d4fd0dc3b45de7b7a706285845ef5b527422014 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 21 Nov 2012 17:02:59 +0000 Subject: mx28: Fix typo in POWER_DCLIMITS_NEGLIMIT_OFFSET The POWER_DCLIMITS_NEGLIMIT_OFFSET bit in mx28 power supply block is not called POWER_DCLIMITS_NETLIMIT_OFFSET, but POWER_DCLIMITS_NEGLIMIT_OFFSET. Correct the name in the header file. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/include/asm/arch-mxs/regs-power.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mxs/regs-power.h b/arch/arm/include/asm/arch-mxs/regs-power.h index 3c98cce..257ee88 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power.h +++ b/arch/arm/include/asm/arch-mxs/regs-power.h @@ -268,7 +268,7 @@ struct mxs_power_regs { #define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) #define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 #define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NETLIMIT_OFFSET 0 +#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 #define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) #define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -- cgit v1.1