From 504b9f1a5fa1c3c7efc8349907703986dcd4ed8a Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 29 Mar 2017 21:20:28 +0200 Subject: rockchip: spl: rk3399: disable DDR security regions for SPL The RK3399 hangs during DMA of the Designware MMC controller, when performing DMA-based transactions in SPL due to the DDR security settings left behind by the BootROM (i.e. accesses to the first MB of DRAM are restricted... however, the DMA is likely to target this first MB, as it transfers from/to the stack). System security is not affected, as the final security configuration is performed by the ATF, which is executed after the SPL stage. With this fix in place, we can now drop 'fifo-mode' in the DTS for the RK3399-Q7 (Puma). Signed-off-by: Philipp Tomsich Reviewed-by: Kever Yang Acked-by: Simon Glass --- arch/arm/mach-rockchip/rk3399-board-spl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 4f84ec1..f546529 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -157,6 +157,7 @@ void secure_timer_init(void) } #define GRF_EMMCCORE_CON11 0xff77f02c +#define SGRF_DDR_RGN_CON16 0xff330040 void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -201,6 +202,17 @@ void board_init_f(ulong dummy) hang(); } + /* + * Disable DDR security regions. + * + * As we are entered from the BootROM, the region from + * 0x0 through 0xfffff (i.e. the first MB of memory) will + * be protected. This will cause issues with the DW_MMC + * driver, which tries to DMA from/to the stack (likely) + * located in this range. + */ + rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0); + secure_timer_init(); ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); @@ -238,6 +250,7 @@ void spl_board_init(void) #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM back_to_bootrom(); #endif + return; err: printf("spl_board_init: Error %d\n", ret); -- cgit v1.1 From 35d1b6dc08b6b1ed39ce5039df731ec0032ba6b2 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 29 Mar 2017 21:20:29 +0200 Subject: rockchip: dts: rk3399-puma: disable 'fifo-mode' in sdmmc Signed-off-by: Philipp Tomsich Acked-by: Simon Glass --- arch/arm/dts/rk3399-puma.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts index 917df1e..71eb72d 100644 --- a/arch/arm/dts/rk3399-puma.dts +++ b/arch/arm/dts/rk3399-puma.dts @@ -91,7 +91,6 @@ &sdmmc { u-boot,dm-pre-reloc; bus-width = <4>; - fifo-mode; /* until we fix DMA in SPL */ status = "okay"; }; -- cgit v1.1 From 6499b1976cb90734a76fdf979f530741251e4978 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 6 Apr 2017 00:19:18 +0200 Subject: rockchip: cosmetic: Move rock board to its correct position Somehow 43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") moved the rock board in between some rk3288 board, probably as a result of rebasing. So move it back to its original position above all rk3288 boards. Fixes: 43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") Signed-off-by: Heiko Stuebner Acked-by: Simon Glass --- arch/arm/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 68d2791..ce34e3e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -29,12 +29,12 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-sdk.dtb \ + rk3188-radxarock.dtb \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ rk3288-popmetal.dtb \ - rk3188-radxarock.dtb \ rk3288-rock2-square.dtb \ rk3288-tinker.dtb \ rk3288-veyron-jerry.dtb \ -- cgit v1.1 From 008a610b4cb1a3e55369c6c1f1060c892a81422c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 6 Apr 2017 00:19:36 +0200 Subject: rockchip: rk3188: enable remap function Most Rockchip socs have the ability to either map the bootrom or a sram area to the starting address of the cpu by flipping a bit in the GRF. Newer socs leave this untouched and mapped to the bootrom but the legacy loaders on rk3188 and before enabled the remap functionality and the current smp implementation in the Linux kernel also requires it to be enabled, to bring up secondary cpus. So to keep smp working in the kernel, mimic the behaviour of the legacy bootloaders and enable the remap functionality. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3188-board.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index af0796d..5b4caec 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -18,6 +18,7 @@ config ROCKCHIP_RK3188 select SUPPORT_TPL select SPL select TPL + select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index c370156..4be711e 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,23 @@ DECLARE_GLOBAL_DATA_PTR; +int board_late_init(void) +{ + struct rk3188_grf *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(grf)) { + error("grf syscon returned %ld\n", PTR_ERR(grf)); + } else { + /* enable noc remap to mimic legacy loaders */ + rk_clrsetreg(&grf->soc_con0, + NOC_REMAP_MASK << NOC_REMAP_SHIFT, + NOC_REMAP_MASK << NOC_REMAP_SHIFT); + } + + return 0; +} + int board_init(void) { #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) -- cgit v1.1 From faf1afc4734c4b886c1359dc9b390aa2aceefb62 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Fri, 7 Apr 2017 19:09:37 +0200 Subject: rockchip: dts: rk3399-puma: make the DTS dual-licensed The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed. This updates the licensing info in the rk3399-puma.dts. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- arch/arm/dts/rk3399-puma.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts index 71eb72d..50e43c7 100644 --- a/arch/arm/dts/rk3399-puma.dts +++ b/arch/arm/dts/rk3399-puma.dts @@ -1,7 +1,7 @@ /* * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -- cgit v1.1 From a13110a99fffb431db60ec5b50e263d0bd2b811d Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Fri, 7 Apr 2017 19:13:38 +0200 Subject: rockchip: ARM64: split RK3399-Q7 board off the RK3399-EVB board The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3399. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit interace) * SD card (on a baseboad) via edge connector * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI displays * 2x MIPI-CSI * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub) * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Note that we use a multi-payload FIT image for booting and have Cortex-M0 payload in a separate subimage: we thus rely on the FIT image loader to put it into the SRAM region that ATF expects it in. Signed-off-by: Klaus Goger Signed-off-by: Philipp Tomsich Fixed build warning on puma-rk3399: Signed-off-by: Simon Glass Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/rk3399/Kconfig | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 83bd04a..415466a 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -10,6 +10,24 @@ config TARGET_EVB_RK3399 with full function and phisical connectors support like type-C ports, usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... +config TARGET_PUMA_RK3399 + bool "Theobroma Systems RK3399-Q7 (Puma)" + help + The RK3399-Q7 (Puma) is a system-on-module (designed and + marketed by Theobroma Systems) featuring the Rockchip RK3399 + in a Qseven-compatible form-factor (running of a single 5V + supply and exposing its external interfaces on a MXM-230 + connector). + + Key features of the RK3399-Q7 include: + * on-module USB 3.0 hub (2x USB 3.0 host + 1x USB 2.0 host) + * USB 3.0 dual-role + * on-module Micrel KSZ9031 GbE PHY + * on-module eMMC (up to 256GB configurations available) + * on-module DDR3 (1GB, 2GB and 4GB configurations available) + * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI + * SPI, I2C, I2S, UART, GPIO, ... + endchoice config SYS_SOC @@ -19,5 +37,6 @@ config SYS_MALLOC_F_LEN default 0x0800 source "board/rockchip/evb_rk3399/Kconfig" +source "board/theobroma-systems/puma_rk3399/Kconfig" endif -- cgit v1.1 From bc8e8fe40bc57c7fe0ecafb09e180bdfefe408d5 Mon Sep 17 00:00:00 2001 From: "eric.gao@rock-chips.com" Date: Mon, 10 Apr 2017 09:53:31 +0800 Subject: rockchip: rk3399: Add missing sentinel in syscon when enable PMIC rk808,the system will halt at very early stage,log is shown as bellow. INFO: plat_rockchip_pmu_init(1211): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 time 44561b, 0 (<<----Just stop here) It's caused by the absence of "{ }" in syscon_rk3399.c ,which will lead to memory overflow like below.According to Sysmap file ,we can find the function buck_get_value of rk808 is just follow the compatible struct,the pointer "of_match" point to "buck_get_value",but it is not a struct and don't have member of compatible, In this case, system crash. So,on the face, it looks like that rk808 is guilty.but he is really innocent. while (of_match->compatible) { <<---------- if (!strcmp(of_match->compatible, compat)) { *of_idp = of_match; return 0; } of_match++; } Signed-off-by: Eric Gao Reviewed-by: Kever Yang Tested-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index d32985b..74d4552 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -14,6 +14,7 @@ static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, { .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF }, { .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC }, + { } }; U_BOOT_DRIVER(syscon_rk3399) = { -- cgit v1.1 From b644354a7c255defe0086c15ccb6b298f27a8bcf Mon Sep 17 00:00:00 2001 From: "eric.gao@rock-chips.com" Date: Mon, 10 Apr 2017 10:17:03 +0800 Subject: rockchip: i2c: Enable i2c for rk3399 To enable mipi display, we need to enable pmic rk808 first for lcd3v3 power,which use i2c0 to communicate with soc. So enable i2c0. Signed-off-by: Eric Gao Acked-by: Simon Glass --- arch/arm/dts/rk3399.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index dbe55f2..d94d780 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -26,6 +26,7 @@ serial4 = &uart4; mmc0 = &sdhci; mmc1 = &sdmmc; + i2c0 = &i2c0; }; cpus { @@ -668,6 +669,21 @@ status = "disabled"; }; + i2c0: i2c@ff3c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3c0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C0_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl"; -- cgit v1.1 From d3cf9eb2d87c8961408ec5aa6ebe0c54f2c13724 Mon Sep 17 00:00:00 2001 From: "eric.gao@rock-chips.com" Date: Mon, 10 Apr 2017 10:41:46 +0800 Subject: rockchip: pmic: Enable RK808 for rk3399 evb For using mipi display, we need to enable lcd3v3 which supplied by rk808,so enable rk808 first. Signed-off-by: Eric Gao Acked-by: Simon Glass --- arch/arm/dts/rk3399-evb.dts | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index c3a7ca2..e1f867b 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -30,6 +30,13 @@ status = "okay"; }; + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vccsys"; + regulator-boot-on; + regulator-always-on; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -51,6 +58,7 @@ regulator-name = "vcc5v0_host"; gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; }; + }; &emmc_phy { @@ -112,6 +120,37 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <100>; + u-boot,dm-pre-reloc; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + clock-output-names = "xin32k", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + reg = <0x1b>; + rockchip,system-power-controller; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + status = "okay"; + + vcc12-supply = <&vcc3v3_sys>; + regulators { + vcc33_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_lcd"; + }; + }; + }; +}; + &pinctrl { pmic { pmic_int_l: pmic-int-l { -- cgit v1.1 From 7ee16de58bddaa9619c264313008d7e19300b42a Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Sat, 1 Apr 2017 12:59:25 +0200 Subject: rockchip: rk3399: spl: add UART0 support for SPL The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the serial line available via standardised pins on the edge connector and available on a RS232 connector). To support boards (such as the RK3399-Q7) that require UART0 as a debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate iomux setup to the rk3399 SPL code. As we are already touching this code, we also move the board-specific UART setup (i.e. iomux setup) into board_debug_uart_init(). This will be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT is set. As the RK3399 needs to use its board_debug_uart_init() function, we have Kconfig enable it by default for RK3399 builds. With everything set up to define CONFIG_BAUDRATE via defconfig and with to have the SPL debug UART either on UART0 or UART2, the configs for the RK3399 EVB are then update (the change for the RK3399-Q7 is left for later to not cause issues on applying the change). Signed-off-by: Philipp Tomsich Reviewed-by: Kever Yang Acked-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 8 +++++++ arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3399-board-spl.c | 30 ++++++++++++++++++------- 3 files changed, 31 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index b340b05..c424753 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -337,6 +337,14 @@ enum { GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, GRF_SPI2TPM_CSN0 = 1, + /* GRF_GPIO2C_IOMUX */ + GRF_GPIO2C0_SEL_SHIFT = 0, + GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT, + GRF_UART0BT_SIN = 1, + GRF_GPIO2C1_SEL_SHIFT = 2, + GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT, + GRF_UART0BT_SOUT = 1, + /* GRF_GPIO3A_IOMUX */ GRF_GPIO3A0_SEL_SHIFT = 0, GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 5b4caec..2b752ad 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -56,6 +56,7 @@ config ROCKCHIP_RK3399 select SPL select SPL_SEPARATE_BSS select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index f546529..050f5e1 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -156,20 +156,24 @@ void secure_timer_init(void) writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } -#define GRF_EMMCCORE_CON11 0xff77f02c #define SGRF_DDR_RGN_CON16 0xff330040 -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl; - struct udevice *dev; - int ret; - /* Example code showing how to enable the debug UART on RK3288 */ +void board_debug_uart_init(void) +{ #include - /* Enable early UART2 channel C on the RK3399 */ #define GRF_BASE 0xff770000 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3399 */ + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C0_SEL_MASK, + GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C1_SEL_MASK, + GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); +#else + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); @@ -180,6 +184,16 @@ void board_init_f(ulong dummy) rk_clrsetreg(&grf->soc_con7, GRF_UART_DBG_SEL_MASK, GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); +#endif +} + +#define GRF_EMMCCORE_CON11 0xff77f02c +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + #define EARLY_UART #ifdef EARLY_UART /* -- cgit v1.1