From de9b1771c3b663509102aa05b4275949da69f998 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 23 Aug 2017 12:03:41 +0200 Subject: mmc: sunxi: Support new mode Almost all of the newer Allwinner SoCs have a new operating mode for the eMMC clocks that needs to be enabled in both the clock and the MMC controller. Details about that mode are sparse, and the name itself (new mode vs old mode) doesn't give much details, but it seems that the it changes the sampling of the MMC clock. One side effect is also that it divides the parent clock rate by 2. Add support for it through a Kconfig option. Signed-off-by: Maxime Ripard Reviewed-by: Jagan Teki --- arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 1 + arch/arm/include/asm/arch-sunxi/mmc.h | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 5e1346e..5dfcbf3 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -220,6 +220,7 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) #define CCM_MMC_CTRL_OSCM24 (0x0 << 24) #define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_MODE_SEL_NEW (0x1 << 30) #define CCM_MMC_CTRL_ENABLE (0x1 << 31) #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index cb52e64..69f737f 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -35,16 +35,19 @@ struct sunxi_mmc { u32 cbcr; /* 0x48 CIU byte count */ u32 bbcr; /* 0x4c BIU byte count */ u32 dbgc; /* 0x50 debug enable */ - u32 res0[11]; + u32 res0; /* 0x54 reserved */ + u32 a12a; /* 0x58 Auto command 12 argument */ + u32 ntsr; /* 0x5c New timing set register */ + u32 res1[8]; u32 dmac; /* 0x80 internal DMA control */ u32 dlba; /* 0x84 internal DMA descr list base address */ u32 idst; /* 0x88 internal DMA status */ u32 idie; /* 0x8c internal DMA interrupt enable */ u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ - u32 res1[26]; + u32 res2[26]; #ifdef CONFIG_SUNXI_GEN_SUN6I - u32 res2[64]; + u32 res3[64]; #endif u32 fifo; /* 0x100 / 0x200 FIFO access address */ }; @@ -116,6 +119,8 @@ struct sunxi_mmc { #define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) #define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) +#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) + #define SUNXI_MMC_IDMAC_RESET (0x1 << 0) #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) -- cgit v1.1 From 343ff161062880c5112b014c9181694bd01ee886 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 23 Aug 2017 12:03:42 +0200 Subject: sunxi: Enable MMC new mode for A83T The eMMC controller for the A83T uses the new operating mode. Enable it. Signed-off-by: Maxime Ripard Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 2cd7bae..2309f59 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -125,6 +125,7 @@ config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7 select SUNXI_GEN_SUN6I + select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL config MACH_SUN8I_H3 -- cgit v1.1