From da880bf7c18041e598def664c641705208359dfa Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Thu, 30 Mar 2023 20:24:22 +0200 Subject: ARM: dts: trimslice: sync SPI node with Linux dts After "spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode" series flash speed and mode wasn't passed to driver anymore, which resulted in: Loading Environment from SPIFlash... tegra20_sflash spi@7000c380: Invalid chip select 0:0 (err=-19) *** Warning - spi_flash_probe_bus_cs() failed, using default environment Fix it by syncing SPI node of affected device dts with Linux kernel dts. The changed SPI bus frequency doesn't influence stability of read/write operations. Ref: https://patchwork.ozlabs.org/project/uboot/cover/20220518064648.1843664-1-patrice.chotard@foss.st.com Signed-off-by: Tomasz Maciej Nowak Signed-off-by: Tom --- arch/arm/dts/tegra20-trimslice.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index e19001e..fa942d2 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -27,7 +27,13 @@ spi@7000c380 { status = "okay"; - spi-max-frequency = <25000000>; + spi-max-frequency = <48000000>; + + flash@0 { + compatible = "winbond,w25q80bl", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <48000000>; + }; }; pcie@80003000 { -- cgit v1.1 From d83721f1d4a18f576e66264ac5a1812b9a82f008 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 30 Jun 2023 10:29:02 +0300 Subject: ARM: tegra: add SoC UID calculation function This is a small tool for calculation of SoC UID based on the same Linux function. It can be further used for generation of device unique data like mac address or exposing it as serial number. Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565 Tested-by: Svyatoslav Ryhel # LG P895 T30 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/include/asm/arch-tegra/fuse.h | 7 ++ arch/arm/mach-tegra/Makefile | 4 + arch/arm/mach-tegra/fuse.c | 151 +++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 arch/arm/mach-tegra/fuse.c (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h index 5b8e0bd..f3f2ad8 100644 --- a/arch/arm/include/asm/arch-tegra/fuse.h +++ b/arch/arm/include/asm/arch-tegra/fuse.h @@ -19,4 +19,11 @@ struct fuse_regs { u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ }; +/** + * Calculate SoC UID + * + * Return: uid if ok, 0 on error + */ +unsigned long long tegra_chip_uid(void); + #endif /* ifndef _FUSE_H_ */ diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 9147050..a5733b0 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -32,6 +32,10 @@ endif obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-y += pmc.o +ifndef CONFIG_TEGRA186 +obj-y += fuse.o +endif + obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ obj-$(CONFIG_TEGRA114) += tegra114/ diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c new file mode 100644 index 0000000..83bd505 --- /dev/null +++ b/arch/arm/mach-tegra/fuse.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2012-2013 + * NVIDIA Corporation + * + * (C) Copyright 2022 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include "cpu.h" + +#define FUSE_UID_LOW 0x108 +#define FUSE_UID_HIGH 0x10c + +#define FUSE_VENDOR_CODE 0x200 +#define FUSE_FAB_CODE 0x204 +#define FUSE_LOT_CODE_0 0x208 +#define FUSE_LOT_CODE_1 0x20c +#define FUSE_WAFER_ID 0x210 +#define FUSE_X_COORDINATE 0x214 +#define FUSE_Y_COORDINATE 0x218 + +#define FUSE_VENDOR_CODE_MASK 0xf +#define FUSE_FAB_CODE_MASK 0x3f +#define FUSE_WAFER_ID_MASK 0x3f +#define FUSE_X_COORDINATE_MASK 0x1ff +#define FUSE_Y_COORDINATE_MASK 0x1ff + +static u32 tegra_fuse_readl(unsigned long offset) +{ + return readl(NV_PA_FUSE_BASE + offset); +} + +static void tegra_fuse_init(void) +{ + u32 reg; + + /* + * Performed by downstream and is not + * documented by TRM. Whithout setting + * this bit fuse region will not work. + */ + reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48); + reg |= BIT(28); + writel(reg, NV_PA_CLK_RST_BASE + 0x48); + + clock_enable(PERIPH_ID_FUSE); + udelay(2); + reset_set_enable(PERIPH_ID_FUSE, 0); +} + +unsigned long long tegra_chip_uid(void) +{ + u64 uid = 0ull; + u32 reg; + u32 cid; + u32 vendor; + u32 fab; + u32 lot; + u32 wafer; + u32 x; + u32 y; + u32 i; + + tegra_fuse_init(); + + /* This used to be so much easier in prior chips. Unfortunately, there + is no one-stop shopping for the unique id anymore. It must be + constructed from various bits of information burned into the fuses + during the manufacturing process. The 64-bit unique id is formed + by concatenating several bit fields. The notation used for the + various fields is with the UID composed + thusly: + + Where: + Field Bits Position Data + ------- ---- -------- ---------------------------------------- + CID 4 60 Chip id + VENDOR 4 56 Vendor code + FAB 6 50 FAB code + LOT 26 24 Lot code (5-digit base-36-coded-decimal, + re-encoded to 26 bits binary) + WAFER 6 18 Wafer id + X 9 9 Wafer X-coordinate + Y 9 0 Wafer Y-coordinate + ------- ---- + Total 64 + */ + + switch (tegra_get_chip()) { + case CHIPID_TEGRA20: + /* T20 has simple calculation */ + return ((unsigned long long)tegra_fuse_readl(FUSE_UID_HIGH) << 32ull) | + (unsigned long long)tegra_fuse_readl(FUSE_UID_LOW); + case CHIPID_TEGRA30: + /* T30 chip id is 0 */ + cid = 0; + break; + case CHIPID_TEGRA114: + /* T11x chip id is 1 */ + cid = 1; + break; + case CHIPID_TEGRA124: + /* T12x chip id is 3 */ + cid = 3; + break; + case CHIPID_TEGRA210: + /* T210 chip id is 5 */ + cid = 5; + default: + return 0; + } + + vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK; + fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK; + + /* Lot code must be re-encoded from a 5 digit base-36 'BCD' number + to a binary number. */ + lot = 0; + reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2; + + for (i = 0; i < 5; ++i) { + u32 digit = (reg & 0xFC000000) >> 26; + lot *= 36; + lot += digit; + reg <<= 6; + } + + wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK; + x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK; + y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK; + + uid = ((unsigned long long)cid << 60ull) + | ((unsigned long long)vendor << 56ull) + | ((unsigned long long)fab << 50ull) + | ((unsigned long long)lot << 24ull) + | ((unsigned long long)wafer << 18ull) + | ((unsigned long long)x << 9ull) + | ((unsigned long long)y << 0ull); + + return uid; +} -- cgit v1.1 From 15be9a7b3b08fa11d046162aaeb899e5d726cb90 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 30 Jun 2023 10:29:03 +0300 Subject: board: asus: transformer: add ASUS Transformer T30 family support The ASUS Transformer T30 family are 2-in-1 detachable tablets and AiO developed by ASUS that run the Android operating system (TF600T runs Windows RT and P1801-T runs Android and Windows). The T30 Transformers feature a 10.1-inch display (apart P1801-T), an Nvidia Tegra 3 quad-core chip, 1/2 GB of RAM, and 16/32 GB of storage. Transformers board derives from Nvidia Cardhu development board. This patch brings support for 7 known Transformer devices: - ASUS Transformer Prime TF201 - ASUS Transformer Pad TF300T/TF300TG/TF300TL - ASUS VivoTab RT TF600T (Windows RT based) - ASUS Transformer Infinity TF700T - ASUS Portable AiO P1801-T Tested-by: Andreas Westman Dorcsak # all devices Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/dts/Makefile | 7 + arch/arm/dts/tegra30-asus-p1801-t.dts | 18 +++ arch/arm/dts/tegra30-asus-tf201.dts | 9 ++ arch/arm/dts/tegra30-asus-tf300t.dts | 18 +++ arch/arm/dts/tegra30-asus-tf300tg.dts | 9 ++ arch/arm/dts/tegra30-asus-tf300tl.dts | 9 ++ arch/arm/dts/tegra30-asus-tf600t.dts | 89 ++++++++++++ arch/arm/dts/tegra30-asus-tf700t.dts | 13 ++ arch/arm/dts/tegra30-asus-transformer.dtsi | 211 +++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra30/Kconfig | 5 + 10 files changed, 388 insertions(+) create mode 100644 arch/arm/dts/tegra30-asus-p1801-t.dts create mode 100644 arch/arm/dts/tegra30-asus-tf201.dts create mode 100644 arch/arm/dts/tegra30-asus-tf300t.dts create mode 100644 arch/arm/dts/tegra30-asus-tf300tg.dts create mode 100644 arch/arm/dts/tegra30-asus-tf300tl.dts create mode 100644 arch/arm/dts/tegra30-asus-tf600t.dts create mode 100644 arch/arm/dts/tegra30-asus-tf700t.dts create mode 100644 arch/arm/dts/tegra30-asus-transformer.dtsi (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269f..c87729d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -237,6 +237,13 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-ventana.dtb \ tegra20-colibri.dtb \ tegra30-apalis.dtb \ + tegra30-asus-p1801-t.dtb \ + tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf300tl.dtb \ + tegra30-asus-tf600t.dtb \ + tegra30-asus-tf700t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ tegra30-colibri.dtb \ diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts new file mode 100644 index 0000000..4b2dc61 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Portable AiO P1801-T"; + compatible = "asus,p1801-t", "nvidia,tegra30"; + + /delete-node/ host1x@50000000; + /delete-node/ pwm@7000a000; + + /delete-node/ backlight; + /delete-node/ panel; + + /delete-node/ regulator-pnl; + /delete-node/ regulator-bl; +}; diff --git a/arch/arm/dts/tegra30-asus-tf201.dts b/arch/arm/dts/tegra30-asus-tf201.dts new file mode 100644 index 0000000..54f359e --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf201.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Prime TF201"; + compatible = "asus,tf201", "nvidia,tegra30"; +}; diff --git a/arch/arm/dts/tegra30-asus-tf300t.dts b/arch/arm/dts/tegra30-asus-tf300t.dts new file mode 100644 index 0000000..db08488 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf300t.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Pad TF300T"; + compatible = "asus,tf300t", "nvidia,tegra30"; + + gpio@6000d000 { + volume-buttons-hog { + gpio-hog; + gpios = , + ; + output-low; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-tf300tg.dts b/arch/arm/dts/tegra30-asus-tf300tg.dts new file mode 100644 index 0000000..6f42182 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf300tg.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Pad 3G TF300TG"; + compatible = "asus,tf300tg", "nvidia,tegra30"; +}; diff --git a/arch/arm/dts/tegra30-asus-tf300tl.dts b/arch/arm/dts/tegra30-asus-tf300tl.dts new file mode 100644 index 0000000..242f791 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf300tl.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Pad LTE TF300TL"; + compatible = "asus,tf300tl", "nvidia,tegra30"; +}; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts new file mode 100644 index 0000000..c9b8f4f --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS VivoTab RT TF600T"; + compatible = "asus,tf600t", "nvidia,tegra30"; + + aliases { + spi0 = &spi4; + }; + + /delete-node/ host1x@50000000; + + pmic_i2c: i2c@7000d000 { + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + regulators { + vdd_1v2_bl: vdd1 { + regulator-name = "vdd_1v2_backlight"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + /delete-node/ ldo2; + /delete-node/ ldo3; + + /* uSD slot VDDIO */ + vddio_usd: ldo5 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + avdd_dsi_csi: ldo6 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; + }; + + spi4: spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + spi-flash@1 { + compatible = "winbond,w25q32", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + backlight { + power-supply = <&vdd_1v2_bl>; + }; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + /delete-node/ panel; + + vdd_usd: regulator-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /delete-node/ regulator-pnl; + /delete-node/ regulator-bl; +}; diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts new file mode 100644 index 0000000..d530527 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer.dtsi" + +/ { + model = "ASUS Transformer Infinity TF700T"; + compatible = "asus,tf700t", "nvidia,tegra30"; + + /delete-node/ host1x@50000000; + + /delete-node/ panel; +}; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi new file mode 100644 index 0000000..4eee1df --- /dev/null +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#include "tegra30.dtsi" + +/ { + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c1 = &gen1_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3100000>; + }; + }; + }; + }; + + sdmmc1: sdhci@78000000 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* USB via ASUS connector */ + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* Dock's USB port */ + usb3: usb@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 4000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + + hactive = <1280>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + + vactive = <800>; + vfront-porch = <3>; + vback-porch = <12>; + vsync-len = <5>; + }; + }; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 85b8ce2..4f78d0b 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -24,6 +24,10 @@ config TARGET_TEC_NG bool "Avionic Design TEC-NG board" select BOARD_LATE_INIT +config TARGET_TRANSFORMER_T30 + bool "Asus Tegra30 Transformer board" + select BOARD_LATE_INIT + endchoice config SYS_SOC @@ -34,5 +38,6 @@ source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" source "board/toradex/colibri_t30/Kconfig" source "board/avionic-design/tec-ng/Kconfig" +source "board/asus/transformer-t30/Kconfig" endif -- cgit v1.1 From 855ffdfa650aa54edf2bfdd99da50cd6255453b8 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 30 Jun 2023 10:29:04 +0300 Subject: board: asus: grouper: add Google Nexus 7 (2012) support Nexus 7 is a mini tablet computer co-developed by Google and Asus that runs the Android operating system. The Nexus 7 features a 7" display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 8/16 GB of internal storage. This patch brings support for all 3 known ASUS/Google devices: - Nexus 7 (2012) E1565 - Nexus 7 (2012) PM269 - Nexus 7 (2012) 3G - tilapia Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565 Tested-by: Svyatoslav Ryhel # ASUS Grouper E1565 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/dts/Makefile | 3 + arch/arm/dts/tegra30-asus-grouper-common.dtsi | 157 +++++++++++++++++++++ arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts | 43 ++++++ arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts | 36 +++++ arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts | 62 ++++++++ arch/arm/mach-tegra/tegra30/Kconfig | 5 + 6 files changed, 306 insertions(+) create mode 100644 arch/arm/dts/tegra30-asus-grouper-common.dtsi create mode 100644 arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts create mode 100644 arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts create mode 100644 arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c87729d..f2b4044 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -237,6 +237,9 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-ventana.dtb \ tegra20-colibri.dtb \ tegra30-apalis.dtb \ + tegra30-asus-nexus7-grouper-PM269.dtb \ + tegra30-asus-nexus7-grouper-E1565.dtb \ + tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-asus-p1801-t.dtb \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi new file mode 100644 index 0000000..4fa980f --- /dev/null +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#include "tegra30.dtsi" + +/ { + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + nvidia,180-rotation; + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + gpio@6000d000 { + volume-buttons-hog { + gpio-hog; + gpios = , + ; + output-low; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 50000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + + hactive = <800>; + hfront-porch = <24>; + hback-porch = <32>; + hsync-len = <24>; + + vactive = <1280>; + vfront-porch = <5>; + vback-porch = <32>; + vsync-len = <1>; + }; + }; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts new file mode 100644 index 0000000..a98d3e2 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-grouper-common.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; + compatible = "asus,grouper", "nvidia,tegra30"; + + i2c@7000d000 { + pmic: max77663@3c { + compatible = "maxim,max77663"; + reg = <0x3c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo3 { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts new file mode 100644 index 0000000..44ea218 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-grouper-common.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; + compatible = "asus,grouper", "nvidia,tegra30"; + + i2c@7000d000 { + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts new file mode 100644 index 0000000..812d5a1 --- /dev/null +++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-grouper-common.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; + compatible = "asus,tilapia", "nvidia,tegra30"; + + i2c@7000d000 { + pmic: max77663@3c { + compatible = "maxim,max77663"; + reg = <0x3c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo3 { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + }; + }; + }; + + panel { + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <81750000>; + + hactive = <800>; + hfront-porch = <64>; + hback-porch = <128>; + hsync-len = <64>; + + vactive = <1280>; + vfront-porch = <5>; + vback-porch = <2>; + vsync-len = <1>; + }; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 4f78d0b..6cbb73e 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -20,6 +20,10 @@ config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" select BOARD_LATE_INIT +config TARGET_GROUPER + bool "Asus and Google Grouper board" + select BOARD_LATE_INIT + config TARGET_TEC_NG bool "Avionic Design TEC-NG board" select BOARD_LATE_INIT @@ -37,6 +41,7 @@ source "board/toradex/apalis_t30/Kconfig" source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" source "board/toradex/colibri_t30/Kconfig" +source "board/asus/grouper/Kconfig" source "board/avionic-design/tec-ng/Kconfig" source "board/asus/transformer-t30/Kconfig" -- cgit v1.1 From 623a8c812e127c4f008dfbb60f29edc8c7d94e09 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 30 Jun 2023 10:29:05 +0300 Subject: board: lg: x3: add Optimus 4X HD and Optimus Vu support LG X3 is a development board based on Nvidia Tegra 3 SoC on base of which Optimus 4X HD and Optimus Vu were created. Both smartphones feature a 4.7" and 5" panels respectively, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 16/32 GB of internal storage. Optimux 4X HD additionally has a micro SD slot. Tested-by: Andreas Westman Dorcsak # LG P880 T30 Tested-by: Svyatoslav Ryhel # LG P895 T30 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/dts/Makefile | 2 + arch/arm/dts/tegra30-lg-p880.dts | 40 ++++++++ arch/arm/dts/tegra30-lg-p895.dts | 50 ++++++++++ arch/arm/dts/tegra30-lg-x3.dtsi | 180 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra30/Kconfig | 5 + 5 files changed, 277 insertions(+) create mode 100644 arch/arm/dts/tegra30-lg-p880.dts create mode 100644 arch/arm/dts/tegra30-lg-p895.dts create mode 100644 arch/arm/dts/tegra30-lg-x3.dtsi (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f2b4044..f31cabc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -250,6 +250,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ tegra30-colibri.dtb \ + tegra30-lg-p880.dtb \ + tegra30-lg-p895.dtb \ tegra30-tec-ng.dtb \ tegra114-dalmore.dtb \ tegra124-apalis.dtb \ diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts new file mode 100644 index 0000000..81d3643 --- /dev/null +++ b/arch/arm/dts/tegra30-lg-p880.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus 4X HD"; + compatible = "lge,p880", "nvidia,tegra30"; + + aliases { + mmc1 = &sdmmc3; /* uSD slot */ + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "jdi,dx12d100vm0eaa"; + + enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; +}; diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts new file mode 100644 index 0000000..074205d --- /dev/null +++ b/arch/arm/dts/tegra30-lg-p895.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus Vu"; + compatible = "lge,p895", "nvidia,tegra30"; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "hitachi,tx13d100vm0eaa"; + + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + renesas,gamma = <3>; + renesas,inversion; + renesas,contrast; + + vcc-supply = <&vcc_3v0_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + backlight = <&backlight>; + }; + + vcc_3v0_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v0_lcd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + iovcc_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "iovcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi new file mode 100644 index 0000000..922e399 --- /dev/null +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#include "tegra30.dtsi" + +/ { + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c1 = &gen2_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + spi0 = &dsi_spi; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&bridge>; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + backlight: lm3533@36 { + compatible = "ti,lm3533"; + reg = <0x36>; + + enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + default-brightness-level = <128>; + }; + + muic@44 { + compatible = "maxim,max14526-muic"; + reg = <0x44>; + + maxim,ap-usb; + + usif-gpios = <&gpio TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>; + dp2t-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>; + }; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max77663@1c { + compatible = "maxim,max77663"; + reg = <0x1c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + regulators { + vdd_1v8_vio: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_usd: ldo3 { + regulator-name = "vdd_sdmmc3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + dsi_spi: spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + + bridge: bridge-spi@2 { + compatible = "solomon,ssd2825"; + reg = <2>; + + spi-cpol; + spi-cpha; + + spi-max-frequency = <1000000>; + + power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>; + + clocks = <&ssd2825_refclk>; + clock-names = "tx_clk"; + + panel = <&panel>; + }; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + micro_usb: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + ssd2825_refclk: clock-ssd2825 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "ssd2825-refclk"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 6cbb73e..9b1df21 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -32,6 +32,10 @@ config TARGET_TRANSFORMER_T30 bool "Asus Tegra30 Transformer board" select BOARD_LATE_INIT +config TARGET_X3_T30 + bool "LG X3 Tegra30 board" + select BOARD_LATE_INIT + endchoice config SYS_SOC @@ -44,5 +48,6 @@ source "board/toradex/colibri_t30/Kconfig" source "board/asus/grouper/Kconfig" source "board/avionic-design/tec-ng/Kconfig" source "board/asus/transformer-t30/Kconfig" +source "board/lg/x3-t30/Kconfig" endif -- cgit v1.1 From bdf9dead86f06c7d6980c399a4a6339430b531ec Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 30 Jun 2023 10:29:06 +0300 Subject: board: htc: endeavoru: add One X support The HTC One X is a touchscreen-based, slate-sized smartphone designed and manufactured by HTC that runs the Android operating system. The One X features a 4.7" display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and non-extendable 32 GB of internal storage. UART-A is default debug port. Tested-by: Andreas Westman Dorcsak Tested-by: Ion Agorria Tested-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra30-htc-endeavoru.dts | 166 +++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra30/Kconfig | 5 + 3 files changed, 172 insertions(+) create mode 100644 arch/arm/dts/tegra30-htc-endeavoru.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f31cabc..3de10ec 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -250,6 +250,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ tegra30-colibri.dtb \ + tegra30-htc-endeavoru.dtb \ tegra30-lg-p880.dtb \ tegra30-lg-p895.dtb \ tegra30-tec-ng.dtb \ diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts new file mode 100644 index 0000000..c55e193 --- /dev/null +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/* This dts file describes the HTC One X smartphone */ +/* CPU Speedo ID 4, Soc Speedo ID 1, CPU Process: 1, Core Process: 0 */ + +#include + +#include "tegra30.dtsi" + +/ { + model = "HTC One X"; + compatible = "htc,endeavoru", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + nvidia,panel = <&dsia>; + }; + }; + + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel = <&panel>; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + /* Texas Instruments TPS80032 PMIC */ + pmic: tps80032@48 { + compatible = "ti,tps80032"; + reg = <0x48>; + + regulators { + /* DSI VDD */ + avdd_dsi_csi: ldo1 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + micro_usb: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + backlight: backlight { + compatible = "nvidia,tegra-pwm-backlight"; + + nvidia,pwm-source = <1>; + nvidia,default-brightness = <0x8E>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "htc,edge-panel"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_3v3_panel>; + vddio-supply = <&vdd_1v8_panel>; + + backlight = <&backlight>; + }; + + vcore_emmc: regulator-emmc { + compatible = "regulator-fixed"; + regulator-name = "vdd_2v85_sdmmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + gpio = <&gpio TEGRA_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_3v3_panel: regulator-lcm { + compatible = "regulator-fixed"; + regulator-name = "v_lcm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(E, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_1v8_panel: regulator-lcmio { + compatible = "regulator-fixed"; + regulator-name = "v_lcmio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(E, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 9b1df21..3e478b3 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -20,6 +20,10 @@ config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" select BOARD_LATE_INIT +config TARGET_ENDEAVORU + bool "HTC Endeavoru T30 board" + select BOARD_LATE_INIT + config TARGET_GROUPER bool "Asus and Google Grouper board" select BOARD_LATE_INIT @@ -45,6 +49,7 @@ source "board/toradex/apalis_t30/Kconfig" source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" source "board/toradex/colibri_t30/Kconfig" +source "board/htc/endeavoru/Kconfig" source "board/asus/grouper/Kconfig" source "board/avionic-design/tec-ng/Kconfig" source "board/asus/transformer-t30/Kconfig" -- cgit v1.1 From d99873517907b806fe35f5a009c2b729c39d5808 Mon Sep 17 00:00:00 2001 From: Abdellatif El Khlifi Date: Fri, 4 Aug 2023 14:33:37 +0100 Subject: arm64: smccc: add support for SMCCCv1.2 x0-x17 registers add support for x0-x17 registers used by the SMC calls In SMCCC v1.2 [1] arguments are passed in registers x1-x17. Results are returned in x0-x17. This work is inspired from the following kernel commit: arm64: smccc: Add support for SMCCCv1.2 extended input/output registers [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= Signed-off-by: Abdellatif El Khlifi Reviewed-by: Ilias Apalodimas Reviewed-by: Jens Wiklander Reviewed-by: Simon Glass Cc: Tom Rini --- arch/arm/cpu/armv8/smccc-call.S | 57 ++++++++++++++++++++++++++++++++++++++++- arch/arm/lib/asm-offsets.c | 16 ++++++++++++ 2 files changed, 72 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S index dc92b28..93f66d3 100644 --- a/arch/arm/cpu/armv8/smccc-call.S +++ b/arch/arm/cpu/armv8/smccc-call.S @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2015, Linaro Limited - */ + * Copyright 2022-2023 Arm Limited and/or its affiliates + * + * Authors: + * Abdellatif El Khlifi +*/ #include #include #include @@ -45,3 +49,54 @@ ENDPROC(__arm_smccc_smc) ENTRY(__arm_smccc_hvc) SMCCC hvc ENDPROC(__arm_smccc_hvc) + +#ifdef CONFIG_ARM64 + + .macro SMCCC_1_2 instr + /* Save `res` and free a GPR that won't be clobbered */ + stp x1, x19, [sp, #-16]! + + /* Ensure `args` won't be clobbered while loading regs in next step */ + mov x19, x0 + + /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */ + ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] + ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] + ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] + ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] + ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] + ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] + ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] + ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] + ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] + + \instr #0 + + /* Load the `res` from the stack */ + ldr x19, [sp] + + /* Store the registers x0 - x17 into the result structure */ + stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] + stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] + stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] + stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] + stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] + stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] + stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] + stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] + stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] + + /* Restore original x19 */ + ldp xzr, x19, [sp], #16 + ret + .endm + +/* + * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, + * struct arm_smccc_1_2_regs *res); + */ +ENTRY(arm_smccc_1_2_smc) + SMCCC_1_2 smc +ENDPROC(arm_smccc_1_2_smc) + +#endif diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 6de0ce9..181a8ac 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -9,6 +9,11 @@ * generate asm statements containing #defines, * compile this file to assembler, and then extract the * #defines from the assembly-language output. + * + * Copyright 2022-2023 Arm Limited and/or its affiliates + * + * Authors: + * Abdellatif El Khlifi */ #include @@ -90,6 +95,17 @@ int main(void) DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); +#ifdef CONFIG_ARM64 + DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS, offsetof(struct arm_smccc_1_2_regs, a0)); + DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2)); + DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS, offsetof(struct arm_smccc_1_2_regs, a4)); + DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS, offsetof(struct arm_smccc_1_2_regs, a6)); + DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS, offsetof(struct arm_smccc_1_2_regs, a8)); + DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS, offsetof(struct arm_smccc_1_2_regs, a10)); + DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS, offsetof(struct arm_smccc_1_2_regs, a12)); + DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS, offsetof(struct arm_smccc_1_2_regs, a14)); + DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS, offsetof(struct arm_smccc_1_2_regs, a16)); +#endif #endif return 0; -- cgit v1.1 From a09852d862bc203b80368ca671ff36e80bcb510f Mon Sep 17 00:00:00 2001 From: Abdellatif El Khlifi Date: Fri, 4 Aug 2023 14:33:41 +0100 Subject: arm_ffa: introduce sandbox FF-A support Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support Features of the sandbox FF-A support: - Introduce an FF-A emulator - Introduce an FF-A device driver for FF-A comms with emulated Secure World - Provides test methods allowing to read the status of the inspected ABIs The sandbox FF-A emulator supports only 64-bit direct messaging. Signed-off-by: Abdellatif El Khlifi Reviewed-by: Simon Glass Cc: Tom Rini Cc: Ilias Apalodimas Cc: Jens Wiklander Cc: Heinrich Schuchardt --- arch/sandbox/dts/sandbox.dtsi | 9 ++ arch/sandbox/dts/test.dts | 8 ++ arch/sandbox/include/asm/sandbox_arm_ffa.h | 72 ++++++++++++++ arch/sandbox/include/asm/sandbox_arm_ffa_priv.h | 121 ++++++++++++++++++++++++ 4 files changed, 210 insertions(+) create mode 100644 arch/sandbox/include/asm/sandbox_arm_ffa.h create mode 100644 arch/sandbox/include/asm/sandbox_arm_ffa_priv.h (limited to 'arch') diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index f0ee0b3..8aaf911 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -451,6 +451,15 @@ thermal { compatible = "sandbox,thermal"; }; + + arm-ffa-emul { + compatible = "sandbox,arm-ffa-emul"; + + sandbox-arm-ffa { + compatible = "sandbox,arm-ffa"; + }; + }; + }; &cros_ec { diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index b5509ee..f351d5c 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1831,6 +1831,14 @@ extcon { compatible = "sandbox,extcon"; }; + + arm-ffa-emul { + compatible = "sandbox,arm-ffa-emul"; + + sandbox-arm-ffa { + compatible = "sandbox,arm-ffa"; + }; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/sandbox_arm_ffa.h b/arch/sandbox/include/asm/sandbox_arm_ffa.h new file mode 100644 index 0000000..be2790f --- /dev/null +++ b/arch/sandbox/include/asm/sandbox_arm_ffa.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022-2023 Arm Limited and/or its affiliates + * + * Authors: + * Abdellatif El Khlifi + */ + +#ifndef __SANDBOX_ARM_FFA_H +#define __SANDBOX_ARM_FFA_H + +#include + +/* + * This header provides public sandbox FF-A emulator declarations + * and declarations needed by FF-A sandbox clients + */ + +/* UUIDs strings of the emulated services */ +#define SANDBOX_SERVICE1_UUID "ed32d533-4209-99e6-2d72-cdd998a79cc0" +#define SANDBOX_SERVICE2_UUID "ed32d544-4209-99e6-2d72-cdd998a79cc0" + +/* IDs of the emulated secure partitions (SPs) */ +#define SANDBOX_SP1_ID 0x1245 +#define SANDBOX_SP2_ID 0x9836 +#define SANDBOX_SP3_ID 0x6452 +#define SANDBOX_SP4_ID 0x7814 + +/* Invalid service UUID (no matching SP) */ +#define SANDBOX_SERVICE3_UUID "55d532ed-0942-e699-722d-c09ca798d9cd" + +/* Invalid service UUID (invalid UUID string format) */ +#define SANDBOX_SERVICE4_UUID "32ed-0942-e699-722d-c09ca798d9cd" + +/* Number of valid services */ +#define SANDBOX_SP_COUNT_PER_VALID_SERVICE 2 + +/** + * struct ffa_sandbox_data - query ABI state data structure + * @data0_size: size of the first argument + * @data0: pointer to the first argument + * @data1_size>: size of the second argument + * @data1: pointer to the second argument + * + * Used to pass various types of data with different sizes between + * the test cases and the sandbox emulator. + * The data is for querying FF-A ABIs state. + */ +struct ffa_sandbox_data { + u32 data0_size; /* size of the first argument */ + void *data0; /* pointer to the first argument */ + u32 data1_size; /* size of the second argument */ + void *data1; /* pointer to the second argument */ +}; + +/* The sandbox FF-A emulator public functions */ + +/** + * sandbox_query_ffa_emul_state() - Inspect the FF-A ABIs + * @queried_func_id: The FF-A function to be queried + * @func_data: Pointer to the FF-A function arguments container structure + * + * Query the status of FF-A ABI specified in the input argument. + * + * Return: + * + * 0 on success. Otherwise, failure + */ +int sandbox_query_ffa_emul_state(u32 queried_func_id, + struct ffa_sandbox_data *func_data); + +#endif diff --git a/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h b/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h new file mode 100644 index 0000000..b088182 --- /dev/null +++ b/arch/sandbox/include/asm/sandbox_arm_ffa_priv.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022-2023 Arm Limited and/or its affiliates + * + * Authors: + * Abdellatif El Khlifi + */ + +#ifndef __SANDBOX_ARM_FFA_PRV_H +#define __SANDBOX_ARM_FFA_PRV_H + +#include + +/* This header is exclusively used by the Sandbox FF-A driver and emulator */ + +/* Non-secure physical FF-A instance */ +#define NS_PHYS_ENDPOINT_ID (0) + +#define GET_NS_PHYS_ENDPOINT_ID_MASK GENMASK(31, 16) +#define GET_NS_PHYS_ENDPOINT_ID(x) \ + ((u16)(FIELD_GET(GET_NS_PHYS_ENDPOINT_ID_MASK, (x)))) + +/* Helper macro for reading the destination partition ID */ +#define GET_DST_SP_ID_MASK GENMASK(15, 0) +#define GET_DST_SP_ID(x) \ + ((u16)(FIELD_GET(GET_DST_SP_ID_MASK, (x)))) + +/* Helper macro for setting the source partition ID */ +#define PREP_SRC_SP_ID_MASK GENMASK(31, 16) +#define PREP_SRC_SP_ID(x) \ + (FIELD_PREP(PREP_SRC_SP_ID_MASK, (x))) + +/* Helper macro for setting the destination endpoint ID */ +#define PREP_NS_PHYS_ENDPOINT_ID_MASK GENMASK(15, 0) +#define PREP_NS_PHYS_ENDPOINT_ID(x) \ + (FIELD_PREP(PREP_NS_PHYS_ENDPOINT_ID_MASK, (x))) + +/* RX/TX buffers minimum size */ +#define RXTX_BUFFERS_MIN_SIZE (RXTX_4K) +#define RXTX_BUFFERS_MIN_PAGES (1) + +/* MBZ registers info */ + +/* x1-x7 MBZ */ +#define FFA_X1X7_MBZ_CNT (7) +#define FFA_X1X7_MBZ_REG_START (&res->a1) + +/* x4-x7 MBZ */ +#define FFA_X4X7_MBZ_CNT (4) +#define FFA_X4X7_MBZ_REG_START (&res->a4) + +/* x3-x7 MBZ */ +#define FFA_X3X7_MBZ_CNT (5) +#define FFA_X3_MBZ_REG_START (&res->a3) + +/* number of emulated FF-A secure partitions (SPs) */ +#define SANDBOX_PARTITIONS_CNT (4) + +/* Binary data of the emulated services UUIDs */ + +/* service 1 UUID binary data (little-endian format) */ +#define SANDBOX_SERVICE1_UUID_A1 0xed32d533 +#define SANDBOX_SERVICE1_UUID_A2 0x99e64209 +#define SANDBOX_SERVICE1_UUID_A3 0x9cc02d72 +#define SANDBOX_SERVICE1_UUID_A4 0xcdd998a7 + +/* service 2 UUID binary data (little-endian format) */ +#define SANDBOX_SERVICE2_UUID_A1 0xed32d544 +#define SANDBOX_SERVICE2_UUID_A2 0x99e64209 +#define SANDBOX_SERVICE2_UUID_A3 0x9cc02d72 +#define SANDBOX_SERVICE2_UUID_A4 0xcdd998a7 + +/** + * struct ffa_rxtxpair_info - structure hosting the RX/TX buffers flags + * @rxbuf_owned: RX buffer ownership flag (the owner is non secure world) + * @rxbuf_mapped: RX buffer mapping flag + * @txbuf_owned TX buffer ownership flag + * @txbuf_mapped: TX buffer mapping flag + * @rxtx_buf_size: RX/TX buffers size + * + * Hosts the ownership/mapping flags of the RX/TX buffers + * When a buffer is owned/mapped its corresponding flag is set to 1 otherwise 0. + */ +struct ffa_rxtxpair_info { + u8 rxbuf_owned; + u8 rxbuf_mapped; + u8 txbuf_owned; + u8 txbuf_mapped; + u32 rxtx_buf_size; +}; + +/** + * struct sandbox_ffa_emul - emulator data + * + * @fwk_version: FF-A framework version + * @id: u-boot endpoint ID + * @partitions: The partitions descriptors structure + * @pair: The RX/TX buffers pair + * @pair_info: The RX/TX buffers pair flags and size + * @test_ffa_data: The data of the FF-A bus under test + * + * Hosts all the emulated secure world data. + */ +struct sandbox_ffa_emul { + u32 fwk_version; + u16 id; + struct ffa_partitions partitions; + struct ffa_rxtxpair pair; + struct ffa_rxtxpair_info pair_info; +}; + +/** + * ffa_emul_find() - Finds the FF-A emulator + * @dev: the sandbox FF-A device (sandbox-arm-ffa) + * @emulp: the FF-A emulator device (sandbox-ffa-emul) + * Return: + * 0 on success. Otherwise, failure + */ +int ffa_emul_find(struct udevice *dev, struct udevice **emulp); + +#endif -- cgit v1.1 From 0f621ca9b92098ee08b944c5138e398059fcf6ee Mon Sep 17 00:00:00 2001 From: Shenlin Liang Date: Fri, 28 Jul 2023 14:57:44 +0800 Subject: arm64: fsl: layerscape: Remove unused functions Function board_switch_core_volt has not been used since it was defined Signed-off-by: Shenlin Liang Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 577a0b6..3bfdc3f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -575,11 +575,6 @@ int get_core_volt_from_fuse(void) return vdd; } -__weak int board_switch_core_volt(u32 vdd) -{ - return 0; -} - static int setup_core_volt(u32 vdd) { return board_setup_core_volt(vdd); -- cgit v1.1 From 22080e05fc4bcfd8c25474ca3ecfce4814fa486d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Jul 2023 11:15:59 -0600 Subject: x86: spl: Drop unwanted debug() This was left over from some previous debugging. Drop it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/spl.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index b6812bb..55c0615 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -137,7 +137,6 @@ static int x86_spl_init(void) } #ifndef CONFIG_SYS_COREBOOT - log_debug("bss\n"); debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start, (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start); memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); -- cgit v1.1 From ea6eef27caba27f8b92b13dda123623d59947ece Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Jul 2023 11:16:01 -0600 Subject: x86: Run QEMU machine setup in SPL Call the hardware-init function from QEMU from SPL. This allows the video BIOS to operate correctly. Create an x86-wide qemu.h header to avoid having to #ifdef the header in spl.c Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng # qemu-x86_64 --- arch/x86/cpu/qemu/qemu.c | 2 +- arch/x86/include/asm/qemu.h | 14 ++++++++++++++ arch/x86/lib/spl.c | 3 +++ 3 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/qemu.h (limited to 'arch') diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 274978c0..7041455 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -48,7 +48,7 @@ static void enable_pm_ich9(void) pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); } -static void qemu_chipset_init(void) +void qemu_chipset_init(void) { u16 device, xbcs; int pam, i; diff --git a/arch/x86/include/asm/qemu.h b/arch/x86/include/asm/qemu.h new file mode 100644 index 0000000..f1e95ff --- /dev/null +++ b/arch/x86/include/asm/qemu.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generic QEMU header + * + * Copyright 2023 Google LLC + */ + +#ifndef __QEMU_H +#define __QEMU_H + +/* set up the chipset for QEMU so that video can be used */ +void qemu_chipset_init(void); + +#endif diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 55c0615..f99df08 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -291,6 +292,8 @@ void spl_board_init(void) #ifndef CONFIG_TPL preloader_console_init(); #endif + if (IS_ENABLED(CONFIG_QEMU)) + qemu_chipset_init(); if (CONFIG_IS_ENABLED(VIDEO)) { struct udevice *dev; -- cgit v1.1 From 1fa64e155d93a9e8a44b34e22390db61bfb24afd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Jul 2023 11:16:02 -0600 Subject: Revert "x86: Switch QEMU over to use the bochs driver" Unfortunately the bochs driver does not currently work with distros. It causes a hang between grub menu selection and the OS displaying something. Preliminary investigation shows that GRUB does not jump to the kernel at all. This reproduces reliably. This reverts commit b8956425d525c3c25fd218f252f89a5e44df6a9f. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng # qemu-x86_64 [Slightly modify the commit message about preliminary investigation] Signed-off-by: Bin Meng --- arch/x86/cpu/qemu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index aa329b0..f8f2f64 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -12,7 +12,7 @@ config QEMU imply SYS_NS16550 imply USB imply USB_EHCI_HCD - imply VIDEO_BOCHS + imply VIDEO_VESA if QEMU -- cgit v1.1 From 4099df48a68fdfdc4b1d57a503679b35e724de4e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Jul 2023 11:16:04 -0600 Subject: x86: Correct copying of BIOS mode information This is copying beyond the end of the destination buffer. Correct the code by using the size of the vesa_mode_info struct. We don't need to copy the rest of the bytes in the buffer. This long-standing bug prevents virtio bootdevs working correctly on qemu-x86 at present. Fixes: 0ca2426beae ("x86: Add support for running option ROMs natively") Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng # qemu-x86_64 --- arch/x86/lib/bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index e29cae7..f146bbd 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -204,7 +204,7 @@ static u8 vbe_get_mode_info(struct vesa_state *mi) realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, 0x0000, buffer_seg, buffer_adr); - memcpy(mi->mode_info_block, buffer, sizeof(struct vesa_state)); + memcpy(mi->mode_info_block, buffer, sizeof(struct vesa_mode_info)); mi->valid = true; return 0; -- cgit v1.1 From edd53bda53b9489aafe6b728b2b71044bb92f248 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Jul 2023 21:01:47 -0600 Subject: x86: Drop CFG_SYS_STACK_SIZE This is only used in one file and the value is the same for both boards which define it. Use the fixed value of 32KB and drop the CFG. This will allow removal of the config.h files. Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko # Intel Edison Reviewed-by: Bin Meng --- arch/x86/lib/physmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index 1eb97ac..382f768 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -14,6 +14,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -144,7 +145,7 @@ static void x86_phys_memset_page(phys_addr_t map_addr, uintptr_t offset, int c, /* Make sure the window is below U-Boot. */ assert(window + LARGE_PAGE_SIZE < - gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE); + gd->relocaddr - CONFIG_SYS_MALLOC_LEN - SZ_32K); /* Map the page into the window and then memset the appropriate part. */ x86_phys_map_page(window, map_addr, 1); memset((void *)(window + offset), c, size); -- cgit v1.1 From dbfb6c096ed1088b3fa2eb9a140393089a3bd731 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Jul 2023 21:01:48 -0600 Subject: x86: i8254: Include required ibmpc.h header This is needed for this file, so include it here explicitly. Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko # Intel Edison Reviewed-by: Bin Meng --- arch/x86/lib/i8254.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c index 0f97538..a8d1db1 100644 --- a/arch/x86/lib/i8254.c +++ b/arch/x86/lib/i8254.c @@ -7,6 +7,7 @@ #include #include #include +#include #define TIMER1_VALUE 18 /* 15.6us */ #define BEEP_FREQUENCY_HZ 440 -- cgit v1.1 From 3cc409536232017cb69a2339c3d9c7e7a3d3d096 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Jul 2023 21:02:04 -0600 Subject: x86: qemu: Add required linux/sizes.h include These files rely on the config.h file provided this include. Add it explictily so we can move to a text environment. Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko # Intel Edison Reviewed-by: Bin Meng --- arch/x86/cpu/qemu/dram.c | 1 + arch/x86/cpu/qemu/e820.c | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index 595c397..1a52d1d 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c index 19e54c5..ebfe595 100644 --- a/arch/x86/cpu/qemu/e820.c +++ b/arch/x86/cpu/qemu/e820.c @@ -12,6 +12,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -- cgit v1.1 From 6982e6b04672440fce0eed93679aea89a024779f Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 2 Aug 2023 22:39:46 +0200 Subject: cmd/sbi: display new extensions The SBI specification v2.0-rc2 defines new extensions: * Nested Acceleration Extension (NACL) * Steal Time Accounting (STA) Allow the sbi command to display these. Add missing implementation IDs. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/sbi.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 7693699..009a268 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -31,6 +31,8 @@ enum sbi_ext_id { SBI_EXT_DBCN = 0x4442434E, SBI_EXT_SUSP = 0x53555350, SBI_EXT_CPPC = 0x43505043, + SBI_EXT_NACL = 0x4E41434C, + SBI_EXT_STA = 0x535441, }; enum sbi_ext_base_fid { -- cgit v1.1 From 1037c5ba3702996d854becb3e719d44d2178c1bf Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Mon, 7 Aug 2023 16:53:36 +0800 Subject: riscv: dts: starfive: Enable pcie0 dts node In StarFive VF2 board. pcie0 connect to VTI usb controller. Enable it to support usb host. Signed-off-by: Minda Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index bf7fdb4..e40f57a 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -311,7 +311,7 @@ &pcie0 { reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; - status = "disabled"; + status = "okay"; }; &pcie1 { -- cgit v1.1 From eca2d41c681466c229fc0b4372432db71745c826 Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Mon, 7 Aug 2023 16:53:37 +0800 Subject: riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive SYS_CACHE_SHIFT_6 to enable it. Signed-off-by: Minda Chen Reviewed-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 4d95811..c1d3e6a 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SYS_CACHE_SHIFT_6 select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD -- cgit v1.1 From d365f6646aa4ecaabc58c07ecc432a3177f13138 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Wed, 9 Aug 2023 21:11:31 +0800 Subject: riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcb..6771d8d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF help Do not enable data cache in SPL. +config SPL_ZERO_MEM_BEFORE_USE + bool "Zero memory before use" + depends on SPL + default n + help + Zero stack/GD/malloc area in SPL before using them, this is needed for + Sifive core devices that uses L2 cache to store SPL. + # board-specific options below source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -- cgit v1.1 From 6419f8e9fdc63ee411e1f012d412f8ae17283432 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Wed, 9 Aug 2023 21:11:32 +0800 Subject: riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove existing Starfive JH7110's L2 LIM clean code, since existing code has following issues: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing "board_init_f_init_reserve", while other harts are in the middle of zeroing L2 LIM. (data-race) Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/spl.c | 25 ------------------------- arch/riscv/cpu/start.S | 12 ++++++++++++ 2 files changed, 12 insertions(+), 25 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 72adcef..4047b10 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -13,7 +13,6 @@ #include #define CSR_U74_FEATURE_DISABLE 0x7c1 -#define L2_LIM_MEM_END 0x81FFFFFUL DECLARE_GLOBAL_DATA_PTR; @@ -59,9 +58,6 @@ int spl_soc_init(void) void harts_early_init(void) { - ulong *ptr; - u8 *tmp; - ulong len, remain; /* * Feature Disable CSR * @@ -70,25 +66,4 @@ void harts_early_init(void) */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) csr_write(CSR_U74_FEATURE_DISABLE, 0); - - /* clear L2 LIM memory - * set __bss_end to 0x81FFFFF region to zero - * The L2 Cache Controller supports ECC. ECC is applied to SRAM. - * If it is not cleared, the ECC part is invalid, and an ECC error - * will be reported when reading data. - */ - ptr = (ulong *)&__bss_end; - len = L2_LIM_MEM_END - (ulong)&__bss_end; - remain = len % sizeof(ulong); - len /= sizeof(ulong); - - while (len--) - *ptr++ = 0; - - /* clear the remain bytes */ - if (remain) { - tmp = (u8 *)ptr; - while (remain--) - *tmp++ = 0; - } } diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 59d58a5..30cf674 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,6 +111,18 @@ call_board_init_f: * It's essential before any function call, otherwise, we get data-race. */ +/* clear stack if necessary */ +#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE) +clear_stack: + li t1, 1 + slli t1, t1, CONFIG_STACK_SIZE_SHIFT + sub t1, sp, t1 +clear_stack_loop: + SREG zero, 0(t1) /* t1 is always 16 byte aligned */ + addi t1, t1, REGBYTES + blt t1, sp, clear_stack_loop +#endif + call_board_init_f_0: /* find top of reserve space */ #if CONFIG_IS_ENABLED(SMP) -- cgit v1.1 From 47ed15125cccd98e041cdff3b6bbe675a2418ec2 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Wed, 9 Aug 2023 21:11:33 +0800 Subject: riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index c1d3e6a..8469ee7 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -14,6 +14,7 @@ config STARFIVE_JH7110 select SPL_RAM if SPL select SPL_STARFIVE_DDR select SYS_CACHE_SHIFT_6 + select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD -- cgit v1.1 From e5422ea51290db9de0d3a48ec4bfbdf6d27c2662 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 22 Jul 2022 12:09:08 +0200 Subject: rockchip: rk3399: remove duplicate call to regulators_enable_boot_on An earlier commit makes the common SPL code call regulators_enable_boot_on and regulators_enable_boot_off before iterating over possible boot media for U-Boot proper. There is therefore no need to do this in the rk3399-specific code, so let's remove it. Cc: Quentin Schulz Tested-by: Xavier Drudis Ferran Signed-off-by: Quentin Schulz Reviewed-by: Jagan Teki --- arch/arm/mach-rockchip/rk3399/rk3399.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index a7cc91a..cbd2ea0 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -280,15 +280,5 @@ void spl_board_init(void) if (cru->glb_rst_st != 0) rk3399_force_power_on_reset(); } - - if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) { - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - if (regulators_enable_boot_on(false)) - debug("%s: Cannot enable boot on regulator\n", - __func__); - } } #endif -- cgit v1.1 From 080030f2766246bc9b0b41ba9b832b6ed6cb2838 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 14 Jun 2023 13:43:13 +0100 Subject: rockchip: dts: rk3328: Add rng details to u-boot.dtsi Add the rk3328 rng details to the u-boot.dtsi and enable the RNG on the Rock64 to be able to provide a random seed via UEFI. Signed-off-by: Peter Robinson (Fix typo message) Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-u-boot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index ce96ce4..a9f2536 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -26,6 +26,12 @@ 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; }; + + rng: rng@ff060000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff060000 0x0 0x4000>; + status = "okay"; + }; }; &cru { -- cgit v1.1 From 10e38327f017628f782ae4b104dcd64b3d3aa0fd Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 14 Jun 2023 13:43:14 +0100 Subject: rockchip: dts: rk3328: rock64: Align spi flash entry Align the SPI flash entry with upstream. There's no need to diverge here. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 2 +- arch/arm/dts/rk3328-rock64.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8498543..6904515 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -54,7 +54,7 @@ }; &spi0 { - spi_flash: spiflash@0 { + spi_flash: flash@0 { bootph-all; }; }; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 1b0f7e4..f69a38f 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -345,7 +345,7 @@ &spi0 { status = "okay"; - spiflash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; -- cgit v1.1 From 2fa09b455a73a9bda0c616eaecd5dfafd5c19502 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 29 Jul 2023 19:11:42 +0530 Subject: rockchip: rv1126: Enable fdtoverlay support Add fdtoverlay_addr_r and enable OF_LIBFDT_OVERLAY for the use of DT overlay in RV1126. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 49da93d..a279582 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -359,6 +359,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + imply OF_LIBFDT_OVERLAY imply TPL_DM imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT -- cgit v1.1 From bb38db086c6c7eade690d83aa0d96af8c993b991 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 5 Aug 2023 20:00:11 +0800 Subject: rockchip: rk3568: Add EmbedFire Lubancat 2 support LubanCat2 is a rk3568 based SBC from EmbedFire. Specification: - Rockchip rk3568 - LPDDR4/4X 1/2/4/8 GB - TF scard slot - eMMC 8/32/64/128 GB - Gigabit ethernet x 2 - HDMI out - USB 2.0 Host x 1 - USB 2.0 Type-C OTG x 1 - USB 3.0 Host x 1 - Mini PCIE interface for WIFI/BT module - M.2 key for 2280 NVME - 40 pin header The dts file is sync from linux mainline. Signed-off-by: Andy Yan Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi | 27 ++ arch/arm/dts/rk3568-lubancat-2.dts | 733 +++++++++++++++++++++++++++++ 3 files changed, 761 insertions(+) create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bd51806..64c885d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -178,6 +178,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-soquartz-cm4.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ + rk3568-lubancat-2.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi new file mode 100644 index 0000000..27c6277 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Rockchip Electronics Co., Ltd + * (C) Copyright 2023 Andy Yan + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts new file mode 100644 index 0000000..e653b06 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2.dts @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 EmbedFire + */ + +/dts-v1/; +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "EmbedFire LubanCat 2"; + compatible = "embedfire,lubancat-2", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user-led { + label = "user_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_pin>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + dc_5v: dc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_5v>; + }; + + vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "m2_pcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_m2_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "minipcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_mini_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb20_host: vcc5v0-usb20-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb30_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg_vbus"; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_otg_vbus_en>; + pinctrl-names = "default"; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x22>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x21>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gic { + mbi-ranges = <94 31>, <229 31>, <289 31>; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_m2_pcie>; + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_mini_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm8 { + status = "okay"; +}; + +&pwm9 { + status = "disabled"; +}; + +&pwm10 { + status = "disabled"; +}; + +&pwm14 { + status = "disabled"; +}; + +&spi3 { + pinctrl-0 = <&spi3m1_pins>; + status = "disabled"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&sdhci { + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + supports-emmc; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +/* USB OTG/USB Host_1 USB 2.0 Comb */ +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg_vbus>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Host_2/USB Host_3 USB 2.0 Comb */ +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */ +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + dr_mode = "host"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +/* USB3.0 Host */ +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&pinctrl { + leds { + user_led_pin: user-status-led-pin { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; -- cgit v1.1 From 6e710897aa319cda8aaf18a09290e3fb9b6d015f Mon Sep 17 00:00:00 2001 From: Anton Date: Mon, 7 Aug 2023 10:04:46 +0300 Subject: rockchip: cru: Enable cpu info support for rk3568 Add cru structure definition in head file to support cpu_info driver. Series-version: 2 Series-changes: 2 Format the patch header, add commit message and signature. Signed-off-by: Anton Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/cru.h | 2 ++ arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 13ea4ab..9778790 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -15,6 +15,8 @@ # include #elif defined(CONFIG_ROCKCHIP_RK3399) # include +#elif defined(CONFIG_ROCKCHIP_RK3568) +#include #endif /* CRU_GLB_RST_ST */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 399f19a..76f1ad5 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -106,6 +106,8 @@ struct rk3568_cru { unsigned int emmc_con[2];/* Address Offset: 0x0598 */ }; +#define rockchip_cru rk3568_cru + check_member(rk3568_cru, mode_con00, 0xc0); check_member(rk3568_cru, softrst_con[0], 0x400); -- cgit v1.1 From 6da8400d7ae986ef2a8e0ddb4f39907c6c0666f1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 4 Aug 2023 09:33:59 +0000 Subject: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide, not 5 bits wide as currently defined in CPLL_25M_DIV_MASK. Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 76f1ad5..9c7ddd7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -495,7 +495,7 @@ enum { /* CRU_CLK_SEL81_CON */ CPLL_25M_DIV_SHIFT = 8, - CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT, + CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT, CPLL_50M_DIV_SHIFT = 0, CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT, -- cgit v1.1 From 520fece4cacb294b78ca7e3a25667a6449c7287c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 4 Aug 2023 09:34:01 +0000 Subject: rockchip: rk356x-u-boot: Set max-frequency prop in sdhci node Most board device trees for RK356x set max-frequency = <200000000> in the sdhci node, some boards like Quartz64 do not. This result in an error message due to sdhci driver trying to set a clock rate of 0 instead of the max-frequency value. rockchip_sdhci_probe clk set rate fail! Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A patch to set default max-frequency of sdhci node in linux is planned. Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes, boards already set correct state for these nodes. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk356x-u-boot.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index d21b182..32f687f 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -126,12 +126,11 @@ &sdhci { bootph-pre-ram; - status = "okay"; + max-frequency = <200000000>; }; &sdmmc0 { bootph-pre-ram; - status = "okay"; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE -- cgit v1.1 From 08e74ac3d9c20d29e38c1ec6e50688f978975097 Mon Sep 17 00:00:00 2001 From: Massimo Pegorer Date: Wed, 2 Aug 2023 19:05:23 +0200 Subject: rockchip: spl: Drop useless call to debug_uart_init Since commit 0dba45864b2a ("arm: Init the debug UART") function debug_uart_init is called in crt files _main before calling board_init_f. Therefore, there is no need to call it again inside board_init_f implementation in arm/mach-rockchip/spl.c. Signed-off-by: Massimo Pegorer Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 30be640..a6396b3 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -116,12 +116,10 @@ void board_init_f(ulong dummy) /* * Debug UART can be used from here if required: * - * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ - debug_uart_init(); debug("\nspl:debug uart enabled in %s\n", __func__); #endif -- cgit v1.1 From 36adce73724d53f0a22520af86690381b69518aa Mon Sep 17 00:00:00 2001 From: Massimo Pegorer Date: Wed, 2 Aug 2023 19:05:24 +0200 Subject: rockchip: spl: Drop out of scope debug message related to uart init Debug uart is no more inited in board_init_f function: remove this debug message from board_init_f. If an earliest-as-possible message after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE Kconfig option, instead. Signed-off-by: Massimo Pegorer Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index a6396b3..87280e2 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -112,17 +112,6 @@ void board_init_f(ulong dummy) { int ret; -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug("\nspl:debug uart enabled in %s\n", __func__); -#endif - board_early_init_f(); ret = spl_early_init(); -- cgit v1.1 From 0cd87aac5c89941e711c392d5062da031445ae59 Mon Sep 17 00:00:00 2001 From: Massimo Pegorer Date: Thu, 3 Aug 2023 13:08:12 +0200 Subject: clk: rockchip: rk3308: Support reading UART rate and clock registers Add support to read RK3308 registers used to configure UART clocks, and thus to get UART rate and baudrate. This fixes clock_get_rate returning error on serial device probing. Moreover, there is no need anymore to use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files for all cases where UART is not inited by U-Boot proper or by SPL o by TPL code but by a preliminary external boot phase (for Rock PI S, UART is inited by external TPL). Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 2 -- arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index 09694b4..6141555 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -12,6 +12,4 @@ &uart0 { bootph-all; - clock-frequency = <24000000>; - status = "okay"; }; diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h index 86c906b..84b63e4 100644 --- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h +++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h @@ -189,6 +189,21 @@ enum { DCLK_VOP_DIV_SHIFT = 0, DCLK_VOP_DIV_MASK = 0xff, + /* CRU_CLKSEL_CON10 */ + /* CRU_CLKSEL_CON13 */ + /* CRU_CLKSEL_CON16 */ + /* CRU_CLKSEL_CON19 */ + /* CRU_CLKSEL_CON22 */ + CLK_UART_PLL_SEL_SHIFT = 13, + CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT, + CLK_UART_PLL_SEL_DPLL = 0, + CLK_UART_PLL_SEL_VPLL0, + CLK_UART_PLL_SEL_VPLL1, + CLK_UART_PLL_SEL_480M, + CLK_UART_PLL_SEL_24M, + CLK_UART_DIV_CON_SHIFT = 0, + CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT, + /* CRU_CLK_SEL25_CON */ /* CRU_CLK_SEL26_CON */ /* CRU_CLK_SEL27_CON */ -- cgit v1.1 From c71321c7c6ee2a284dd66b949747e91e9cb75341 Mon Sep 17 00:00:00 2001 From: Massimo Pegorer Date: Thu, 3 Aug 2023 13:08:13 +0200 Subject: dts: rockchip: rk3308: Avoid warning for serial probe on prereloc Make device tree complete and consistent for pre relocation phase. Some nodes are missing, causing warnings to be issued on serial port probing during pre relocation phase (uclass_get_device_by_phandle_id fails when called by pinctrl_select_state_full: none of these failures is fatal nor causing issues). Add to *-u-boot.dtsi all required nodes with the 'bootph-some-ram' attribute. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang --- arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index 6141555..d88dee8 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -13,3 +13,30 @@ &uart0 { bootph-all; }; + +&pinctrl { + bootph-some-ram; + + uart0 { + bootph-some-ram; + }; + rtc { + bootph-some-ram; + }; +}; + +&uart0_xfer { + bootph-some-ram; +}; + +&uart0_cts { + bootph-some-ram; +}; + +&uart0_rts { + bootph-some-ram; +}; + +&rtc_32k { + bootph-some-ram; +}; -- cgit v1.1 From bb89d926fc66fc754915f0300c77815e7db9327f Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 20 Jun 2023 00:43:18 +0200 Subject: =?UTF-8?q?ARM:=20rmobile:=20Update=20little=E2=80=90endian=20byte?= =?UTF-8?q?=20order=20option=20in=20srec=5Fcat=20command?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since srecord v1.60, option "-Little_Endian_CONSTant" is deprecated. Fix the build warnings by updating little‐endian byte order option in srec_cat command when generating loader header. Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- arch/arm/mach-rmobile/Makefile | 55 ++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index fadb6eb..4eddba5 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -25,6 +25,13 @@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ spl/u-boot-spl.srec: spl/u-boot-spl FORCE $(call if_changed,objcopy) +srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"} +ifeq "$(srec_cat_gte_160)" "1" + srec_cat_le_cmd := "-constant-l-e" +else + srec_cat_le_cmd := "-l-e-constant" +endif + ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),) # # The first 6 generate statements generate the R-Car Gen3 SCIF loader header. @@ -52,34 +59,34 @@ quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ -offset -0x13fd0 \ -Output_Block_Size 16 \ - -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \ - -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \ - -generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \ - -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \ - -generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \ - -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \ - -generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \ - -generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \ - -generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \ - -generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \ - -generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \ - -generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \ - -generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \ - -generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \ - -generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \ - -generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \ - -generate 0xe6304028 0xe630402c -l-e-constant 0x54ffffaa 4 \ - -generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f0000 4 + -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) 0xe6304000 4 \ + -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \ + -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) 0xe6304000 4 \ + -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 \ + -generate 0xe6304000 0xe6304004 $(srec_cat_le_cmd) 0xd2bcc000 4 \ + -generate 0xe6304004 0xe6304008 $(srec_cat_le_cmd) 0xb26c0400 4 \ + -generate 0xe6304008 0xe630400c $(srec_cat_le_cmd) 0xb2720001 4 \ + -generate 0xe630400c 0xe6304010 $(srec_cat_le_cmd) 0xb27c0421 4 \ + -generate 0xe6304010 0xe6304014 $(srec_cat_le_cmd) 0xb2710402 4 \ + -generate 0xe6304014 0xe6304018 $(srec_cat_le_cmd) 0xaa0203e0 4 \ + -generate 0xe6304018 0xe630401c $(srec_cat_le_cmd) 0xd28e0003 4 \ + -generate 0xe630401c 0xe6304020 $(srec_cat_le_cmd) 0xa8c11424 4 \ + -generate 0xe6304020 0xe6304024 $(srec_cat_le_cmd) 0xa8811444 4 \ + -generate 0xe6304024 0xe6304028 $(srec_cat_le_cmd) 0xf1004063 4 \ + -generate 0xe6304028 0xe630402c $(srec_cat_le_cmd) 0x54ffffaa 4 \ + -generate 0xe630402c 0xe6304030 $(srec_cat_le_cmd) 0xd61f0000 4 else quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ -Output_Block_Size 16 \ - -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \ - -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \ - -generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \ - -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \ - -generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \ - -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 + -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \ + -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin -- cgit v1.1 From d768dd88552df18d4a0527cf3d6ddd05dc072f02 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 12 Aug 2023 20:16:58 +0200 Subject: common: return type board_get_usable_ram_top board_get_usable_ram_top() returns a physical address that is stored in gd->ram_top. The return type of the function should be phys_addr_t like the current type of gd->ram_top. Signed-off-by: Heinrich Schuchardt --- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-mvebu/arm64-common.c | 2 +- arch/arm/mach-rockchip/sdram.c | 2 +- arch/arm/mach-stm32mp/dram_init.c | 2 +- arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-tegra/board2.c | 2 +- arch/mips/mach-jz47xx/jz4780/jz4780.c | 2 +- arch/mips/mach-octeon/dram.c | 2 +- arch/riscv/cpu/fu540/dram.c | 2 +- arch/riscv/cpu/fu740/dram.c | 2 +- arch/riscv/cpu/generic/dram.c | 2 +- arch/riscv/cpu/jh7110/dram.c | 2 +- arch/x86/cpu/broadwell/sdram.c | 2 +- arch/x86/cpu/coreboot/sdram.c | 2 +- arch/x86/cpu/efi/payload.c | 2 +- arch/x86/cpu/efi/sdram.c | 2 +- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/cpu/qemu/dram.c | 2 +- arch/x86/cpu/quark/dram.c | 2 +- arch/x86/cpu/slimbootloader/sdram.c | 2 +- arch/x86/cpu/tangier/sdram.c | 2 +- arch/x86/include/asm/u-boot-x86.h | 2 +- arch/x86/lib/fsp1/fsp_dram.c | 2 +- arch/x86/lib/fsp2/fsp_dram.c | 2 +- 24 files changed, 24 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index d525488..78b775f 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -333,7 +333,7 @@ phys_size_t get_effective_memsize(void) } } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { ulong top_addr; diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index d3a9573..4c67f1a 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define USABLE_RAM_SIZE 0x80000000ULL -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 1d17a74..99ecbdc 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -216,7 +216,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 80ba5c2..7f37b0d 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -40,7 +40,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { phys_size_t size; phys_addr_t reg; diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 391a65a..78597ad 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -64,7 +64,7 @@ static struct mm_region sunxi_mem_map[] = { }; struct mm_region *mem_map = sunxi_mem_map; -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* Some devices (like the EMAC) have a 32-bit DMA limit. */ if (gd->ram_top > (1ULL << 32)) diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 0df1836..981768b 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -403,7 +403,7 @@ int dram_init_banksize(void) * This function is called before dram_init_banksize(), so we can't simply * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { ulong ram_top; diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index 15d1eff..676c305 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -76,7 +76,7 @@ void board_init_f(ulong dummy) } #endif /* CONFIG_SPL_BUILD */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024); } diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 85cb084..5b1311d 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -77,7 +77,7 @@ phys_size_t get_effective_memsize(void) return UBOOT_RAM_SIZE_MAX; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c index 44e11bd..94d8018 100644 --- a/arch/riscv/cpu/fu540/dram.c +++ b/arch/riscv/cpu/fu540/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c index d6d4a41..8657fcd 100644 --- a/arch/riscv/cpu/fu740/dram.c +++ b/arch/riscv/cpu/fu740/dram.c @@ -20,7 +20,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_64BIT /* diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 44e11bd..94d8018 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 2ad3f20..1a9fa46 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index 1295121..f477d51 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -25,7 +25,7 @@ #include #include -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return mrc_common_board_get_usable_ram_top(total_size); } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index f4ee4cd..26352df 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -27,7 +27,7 @@ unsigned int install_e820_map(unsigned int max_entries, * address, and how far U-Boot is moved by relocation are set in the global * data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { uintptr_t dest_addr = 0; int i; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 19a25dd..d8920ef 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { struct efi_mem_desc *desc, *end; struct efi_entry_memmap *map; diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index f3086db..56f3326 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -11,7 +11,7 @@ DECLARE_GLOBAL_DATA_PTR; -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return (ulong)efi_get_ram_base() + gd->ram_size; } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 0718aef..95a826d 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CMOS_OFFSET_MRC_SEED_S3 156 #define CMOS_OFFSET_MRC_SEED_CHK 160 -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return mrc_common_board_get_usable_ram_top(total_size); } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index 1a52d1d..d83abf0 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -72,7 +72,7 @@ int dram_init_banksize(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return qemu_get_low_memory_size(); } diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 8b1ee2d..ad98f3e 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -184,7 +184,7 @@ int dram_init_banksize(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return gd->ram_size; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index d748d5c..fbb33b2 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -48,7 +48,7 @@ static struct sbl_memory_map_info *get_memory_map_info(void) * @total_size: The memory size that u-boot occupies * Return: : The top available memory address lower than 4GB */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { struct sbl_memory_map_info *data; int i; diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 8a4b1c5..ee74a1f 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -204,7 +204,7 @@ unsigned int install_e820_map(unsigned int max_entries, * address, and how far U-Boot is moved by relocation are set in the global * data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { struct sfi_table_simple *sb; struct sfi_mem_entry *mentry; diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 02a8b0f..3acc58a 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -77,7 +77,7 @@ int x86_cleanup_before_linux(void); void x86_enable_caches(void); void x86_disable_caches(void); int x86_init_cache(void); -phys_size_t board_get_usable_ram_top(phys_size_t total_size); +phys_addr_t board_get_usable_ram_top(phys_size_t total_size); int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index 5825221..eee9ce5 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -34,7 +34,7 @@ int dram_init(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { return fsp_get_usable_lowmem_top(gd->arch.hob_list); } diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index f9ea1ab..a143223 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -77,7 +77,7 @@ int dram_init(void) return 0; } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { if (!ll_boot_init()) return gd->ram_size; -- cgit v1.1 From fc7bd99f6d2d732d70bb2191f69955ea335577c6 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 3 Jul 2023 18:02:33 +0200 Subject: ARM: dts: stm32: fix display pinmux for stm32f746-disco As reported by the datasheet (DocID027590 Rev 4) for PG12: - AF9 -> LCD_B4 - AF14 -> LCD_B1 So replace AF14 with AF9 for PG12 in the dts. Fixes: fe63d3cfb77ef ("ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7") Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 19b5451..522cffb 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -169,7 +169,7 @@ ltdc_pins: ltdc@0 { pins { pinmux = , /* B0 */ - , /* B4 */ + , /* B4 */ , /* VSYNC */ , /* HSYNC */ , /* CLK */ -- cgit v1.1 From b58ab56d14f242850142a49e2a62a80389b3a11e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Jul 2023 23:32:27 +0200 Subject: ARM: stm32: Inhibit PDDS because CSTBYDIS is set The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never enter CStandby state and would always end up in CStop state. Clear the PDDS bit, which indicates the CA cores can enter CStandby state as it makes little sense to keep it set with CSTBYDIS also set. This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR PDDS bits are set, then the chip enters CStandby state even though the PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that from happening. Signed-off-by: Marek Vasut Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/psci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 39b5200..8cdeb0a 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -729,7 +729,7 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); setbits_le32(STM32_PWR_BASE + PWR_MPUCR, - PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); + PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS); saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); -- cgit v1.1 From 61ad1a527a198a3c5ce4cdf25d74108bd038ebb4 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 10 Jul 2023 10:38:45 +0200 Subject: ARM: dts: stm32mp: alignment with v6.4 Device tree alignment with Linux kernel v6.4. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-pinctrl.dtsi | 129 ++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp131.dtsi | 99 ++++++++++++++++++++++++++- arch/arm/dts/stm32mp135f-dk.dts | 42 +++++++++++- arch/arm/dts/stm32mp15-pinctrl.dtsi | 34 +++++----- arch/arm/dts/stm32mp151.dtsi | 4 +- arch/arm/dts/stm32mp157a-dk1.dts | 3 - arch/arm/dts/stm32mp157c-dk2.dts | 3 - arch/arm/dts/stm32mp157c-ed1.dts | 17 ++--- arch/arm/dts/stm32mp157c-ev1.dts | 9 ++- arch/arm/dts/stm32mp15xx-dkx.dtsi | 15 ++--- 10 files changed, 299 insertions(+), 56 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index b2dce3a..27e0c38 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -258,4 +258,133 @@ bias-disable; }; }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = ; /* UART8_TX */ + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = , /* UART8_TX */ + ; /* UART8_RX */ + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_TX */ + , /* USART1_RTS */ + , /* USART1_CTS_NSS */ + ; /* USART1_RX */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index d94ba25..d163c26 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -397,12 +397,42 @@ status = "disabled"; }; + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x5>, + <&dmamux1 46 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; - interrupts = ; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; resets = <&rcc UART4_R>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x5>, + <&dmamux1 64 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x5>, + <&dmamux1 66 0x400 0x1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -442,6 +472,32 @@ status = "disabled"; }; + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x5>, + <&dmamux1 80 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x5>, + <&dmamux1 82 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timers1: timer@44000000 { #address-cells = <1>; #size-cells = <0>; @@ -524,6 +580,19 @@ }; }; + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x5>, + <&dmamux1 72 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s1: audio-controller@44004000 { compatible = "st,stm32h7-i2s"; reg = <0x44004000 0x400>; @@ -748,6 +817,32 @@ status = "disabled"; }; + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s4: audio-controller@4c002000 { compatible = "st,stm32h7-i2s"; reg = <0x4c002000 0x400>; @@ -1001,8 +1096,6 @@ reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - interrupts = ; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; clocks = <&scmi_clk CK_SCMI_HSE>, <&scmi_clk CK_SCMI_HSI>, diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index c40686c..f0900ca 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -19,6 +19,13 @@ aliases { serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; memory@c0000000 { @@ -267,8 +274,41 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + pinctrl-2 = <&usart2_idle_pins_a>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index a9d2bec..e86d989 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1880,6 +1880,21 @@ }; }; + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = , /* SPI2_SCK */ @@ -2163,7 +2178,7 @@ ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins2 { pinmux = , /* USART2_RX */ @@ -2181,7 +2196,7 @@ pinmux = ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins3 { pinmux = ; /* USART2_RX */ @@ -2448,19 +2463,4 @@ bias-disable; }; }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI1_MISO */ - bias-disable; - }; - }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index b3baacb..21d11be 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1148,8 +1148,8 @@ usbotg_hs: usb-otg@49000000 { compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi"; resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = ; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index 4c8be9c..0da3667 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -17,9 +17,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; }; chosen { diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 2bc92ef..ab13e34 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -18,9 +18,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; serial3 = &usart2; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fe5c8f2..3541a17 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -16,6 +16,10 @@ model = "STMicroelectronics STM32MP157C eval daughter"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + aliases { + serial0 = &uart4; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -65,15 +69,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@e8000000 { - reg = <0xe8000000 0x8000000>; - no-map; - }; - }; - - aliases { - serial0 = &uart4; }; sd_switch: regulator-sd_switch { @@ -148,10 +143,6 @@ status = "okay"; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 542226c..ba8e9d9 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -14,16 +14,15 @@ model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { - serial0 = &uart4; serial1 = &usart3; ethernet0 = ðernet0; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + clocks { clk_ext_camera: clk-ext-camera { #clock-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 49b3e76..f4de6c0 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -8,6 +8,12 @@ #include / { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; @@ -53,11 +59,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; }; led { @@ -159,10 +160,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; -- cgit v1.1 From c9678850bdef44bd7cab6238c56151b54d809047 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Jul 2023 01:58:07 +0200 Subject: ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Ported from Linux kernel commit 73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM") Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcom-som.dtsi | 22 ++++++++++++++++++---- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 14 ++++++++++++++ 2 files changed, 32 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index de76174..d3b85a8 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -450,6 +449,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index a808620..f12941b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -153,6 +153,20 @@ }; &rcc { + /* + * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick + * used in stm32mp15xx-dhcom-som.dtsi is not supported by the + * U-Boot clock framework. + */ + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, + <&clk_lse>, <&clk_lsi>; + + /* The MCO2 is already configured correctly, remove those. */ + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P -- cgit v1.1 From dbada49554edd16da39134815635fd0015725c9e Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Fri, 18 Aug 2023 14:17:21 +0100 Subject: arm: rmobile: Fix off-by-one error in cpuinfo In rmobile_cpuinfo_idx() there is an off-by-one error in accessing the rmobile_cpuinfo array. At the end of the loop, i is equal to the array size, i.e. rmobile_cpuinfo[i] accesses one entry past the end of the array. The last entry in the array is a fallback value so the loop should count to ARRAY_SIZE(rmobile_cpuinfo) - 1 instead, this will leave i equal to the index of the fallback value if no match is found. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Marek Vasut --- arch/arm/mach-rmobile/cpu_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 1d33e2a..7651e43 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -86,7 +86,7 @@ static int rmobile_cpuinfo_idx(void) int i = 0; u32 cpu_type = rmobile_get_cpu_type(); - for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) + for (; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++) if (rmobile_cpuinfo[i].cpu_type == cpu_type) break; -- cgit v1.1